Marvell_邁威爾科技有限公司

The Director of Product Engineering for Optics will lead the manufacturing development and continuous improvement needed for the productization of Marvell’s cutting-edge optical products, ranging from Silicon Photonic chip/wafers, pluggable modules and co-packaged optics. This role requires a deep understanding of optical technologies, photonic and electrical IC manufacturing practices, strong leadership skills, and the ability to drive innovation and excellence for volume production. Responsibilities: • Lead and manage the silicon photonics product engineering and test operations group. • Oversee end-to-end Manufacturing solution development for Marvell’s most-advanced silicon photonics products and sub-assemblies, including optical alignment, vendor and new packaging/testing technology development, and contract manufacture bring-up. • Responsible for sustaining and continual improvement in test operations of optical modules, OSAs and Co-packaged Optics. • Collaborate with cross-functional teams, including R&D, Packaging, Quality and external vendors, to drive new product development (NPI) and improvement as well as planning and procurement teams on production ramp and yield issues. • Manage project timelines, budgets, and resources for the silicon photonics product and test operations team to ensure successful product launches. • Mentor and develop team members, fostering a culture of collaboration and continuous improvement to ensure product quality.

Quality and Reliability group are responsible for NPI product qualification, ongoing reliability monitoring, reliability data analysis and life prediction, second source qualification and change qualification, Qualification failure analysis and reliability planning and reporting. We work closely with other functional teams involved in NPI and subsequent product quality. Job Responsibilities: * Work with BU and operations team for NPI requirements planning and technical risk assessments. * Manage multiple product reliability qualifications, from planning to execution and debug. * Coordinate internal and external hardware and engineering resources for reliability qualifications and projects. * Develop qual hardware and its bring-up for qual. * Analyze stress data and results to evaluate the Reliability performance of Logic/Array/Analog Cores IP/Silicon Photonics. * Review and Analyze the ESD/HBM/CDM/LU test results and feedback to design teams for future improvement. * Summarize project findings and results into final qualification reports for customers. * Develop and monitor reliability monitoring programs to establish MTBF, FIT and other reliability metrics. * Drive 8D troubleshooting and root cause analysis of qual failures to improve product reliability. Desired Experience: * Experience in IC quality, product and qualification * Past experience working with 3rd party reliability vendors * Experience with reliability lifetime modelling and calculation * Knowledge for silicon product level reliability qualification and lifetime behavior model. * Knowledge for reliability failure modes of silicon/packaging technologies and failure mechanisms with respect to reliability. * Experience with reliability HW setups and equipment for life, environmental, ESD, Latch-Up, etc., testing. * Experience in second source qualification and bring up.

Analog design engineer responsible for the design, verification, and evaluation of SerDes circuits in high-speed data communication ICs. The responsibilities include but not limited to: * High-speed and high-performance Analog SerDes development in advanced technology nodes, 5nm, 3nm and beyond. * Participate in SerDes design verification across different application and PVT. * Provide the instructions to the layout engineers.

• Responsible for board/chip level silicon validation/characterization on Marvell’s internal IPs such as High-Speed SerDes, PLL, ADC, power regulator, temperature sensor, etc. • Responsible for script development (knowledge of Python, C++, Matlab, Excel VBA is a plus) of automated testing.

* Device characterization * Test program and hardware development.

* Analyze testing data to improve yield * Track major schedule mile-stones. * Design and implement process-oriented and data-driven production methods to guarantee product quality. * Work with Operations and Planning to support on-time delivery according to the production backlog. * Support to provide necessary product engineering support to all customer returns working laterally with Quality engineering in a timely manner.

* Regulatory Compliance: Support the process of ensuring all Marvell products comply with local and international environmental regulations (e.g., RoHS, REACH, TSCA, Prop 65). * Data Management: Maintain and update product environmental compliance documents, including material composition declarations, environmental certifications and ICP reports. * Continuous Improvement: Assist in identifying areas for improvement in product environmental performance and recommend action plans.

• Test program programming/ debugging/ correlation • HVM Release to OSAT. Work with NPI Product & Test Engineering to ensure NPI meets production release requirements and successfully bring up at OSAT. • Set SYL/SBL on new products using product yield history to ensure product quality. • Disposition of production lots and work with NPI Product Engineering to drive yield improvement and test time reduction. • Work with NPI Product & Test Engineering to stabilize and improve product screening at wafer-probe and package levels. • Qualify and manage OSATs for capacity and competitive cost. • Manage OSAT ATE HW inventory and maintain released test programs at OSAT. • Set Quarterly Yield Standards based on yield trends. • Support Supply Chain to meet customer delivery. • Provide special customer requests on assembly and manufacturing related information. • Review and monitor ETest/WAT data to proactively resolve yield issues.

Job Responsibilities: You will be working with global teams in Argentina, Singapore, the U.S., and throughout Europe. You’ll receive a schematic from an Analog IC Designer. You will then take that schematic and use a CAD tool to graphically design the layers of that schematic. Then, you run simulations and verifications on the design using Cadence Virtuoso, refine and debug as needed in concert with the designer, and both of you keep iterating the design until it meets the desired specifications. Each project can last from a couple of months to a year and a half. You will likely work on just one project in that time but may be asked to switch to something else if priorities change. Your flexibility is appreciated. You’ll meet every few days with the designer you’re paired with to share information and work together. No circuits get built or tested here without you both, so your partnership and teamwork are extremely valuable to Marvell. You’ll also have routine meetings with your technical mentor when you have questions, as well as the layout team and the project team where you may have to speak to the entire group and update them about your progress. You may have to present a particular issue or solution you’ve encountered. We are developing brand new cutting-edge technologies here, so we learn new things frequently and share them with our colleagues.

Marvell Packaging Substrate team is a place where you can brainstorm, excel, innovate, transform for the expansion of AI-driven cloud data centers for a once-in-a-lifetime opportunity. As the substrate engineer, you will have the opportunity to work closely with world class substrate suppliers to execute and deliver cutting edge products. You will bring your expertise in optimizing ABF substrate manufacturing/process for solutions and will be responsible for developing advanced ABF substrate materials and technologies to support cutting edge package solutions in all product portfolios. 1. Drill on each substrate process to solve critical substrate technical problems and quality hiccups in NPIs and HVM products. 2. Benchmark, develop, implement new substrate materials into HVM to support advanced node cutting edge silicon products. 3. Define, fine tune, and optimize each ABF substrate manufacturing/process for advanced substrate technology including embedded substrate, MLC, and advanced substrate materials. 4. Be an expert to troubleshoot and support substrate issues on NPIs/HVM and new advanced technology. 5. Interface substrate suppliers and material suppliers to optimize manufacturing/process and control reliability & quality for NPIs and HVM products. 6. Drive NPI design review into timely manufacturing and substrate delivery. 7. Execute substrate cycle time, delivery commitment, substrate qualification & reliability tests. 8. Provide substrate milestones for NPIs into HVM products. 9. Establish the FMEA methodology and spec. 10. Manage substrate suppliers and OSAT substrate team for spec alignment such as substrate parameters & criteria, substrate tray design and selection. 11. Work closely with functional teams including NPI, Quality, Assembly, Test, and BU's. 12. Work with QA, OSAT/substrate suppliers to resolve package related quality/reliability issues.

• Responsible for system-level IP validation such as High-Speed SerDes, PLL, ADC, power regulator, temperature sensor, etc. • Responsible for support on SoC system solutions for PCIe, Ethernet, SATA. SAS and USB. • Responsible for instant troubleshooting and problem-solving for SoC issues using CE IPs. • Responsible for collaborating with chip-level IP validation and design teams for test coverage enhancements.

Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. ASIC design engineer responsible for post-RTL design flow. You will be responsible for block and /or chip-level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to: · Improve the design methodology and flow. · Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. · Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. · Provide support to the product teams, for both pre and post-silicon.