Marvell_邁威爾科技有限公司

Analog design engineer responsible for the design, verification, and evaluation of SerDes circuits in high-speed data communication ICs. The responsibilities include but not limited to: * High-speed and high-performance Analog SerDes development in advanced technology nodes, 5nm, 3nm and beyond. * Participate in SerDes design verification across different application and PVT. * Provide the instructions to the layout engineers.

• Responsible for board/chip level silicon validation/characterization on Marvell’s internal IPs such as High-Speed SerDes, PLL, ADC, power regulator, temperature sensor, etc. • Responsible for script development (knowledge of Python, C++, Matlab, Excel VBA is a plus) of automated testing.

* Device characterization * Test program and hardware development.

* Analyze testing data to improve yield * Track major schedule mile-stones. * Design and implement process-oriented and data-driven production methods to guarantee product quality. * Work with Operations and Planning to support on-time delivery according to the production backlog. * Support to provide necessary product engineering support to all customer returns working laterally with Quality engineering in a timely manner.

• Test program programming/ debugging/ correlation • HVM Release to OSAT. Work with NPI Product & Test Engineering to ensure NPI meets production release requirements and successfully bring up at OSAT. • Set SYL/SBL on new products using product yield history to ensure product quality. • Disposition of production lots and work with NPI Product Engineering to drive yield improvement and test time reduction. • Work with NPI Product & Test Engineering to stabilize and improve product screening at wafer-probe and package levels. • Qualify and manage OSATs for capacity and competitive cost. • Manage OSAT ATE HW inventory and maintain released test programs at OSAT. • Set Quarterly Yield Standards based on yield trends. • Support Supply Chain to meet customer delivery. • Provide special customer requests on assembly and manufacturing related information. • Review and monitor ETest/WAT data to proactively resolve yield issues.

Job Responsibilities: You will be working with global teams in Argentina, Singapore, the U.S., and throughout Europe. You’ll receive a schematic from an Analog IC Designer. You will then take that schematic and use a CAD tool to graphically design the layers of that schematic. Then, you run simulations and verifications on the design using Cadence Virtuoso, refine and debug as needed in concert with the designer, and both of you keep iterating the design until it meets the desired specifications. Each project can last from a couple of months to a year and a half. You will likely work on just one project in that time but may be asked to switch to something else if priorities change. Your flexibility is appreciated. You’ll meet every few days with the designer you’re paired with to share information and work together. No circuits get built or tested here without you both, so your partnership and teamwork are extremely valuable to Marvell. You’ll also have routine meetings with your technical mentor when you have questions, as well as the layout team and the project team where you may have to speak to the entire group and update them about your progress. You may have to present a particular issue or solution you’ve encountered. We are developing brand new cutting-edge technologies here, so we learn new things frequently and share them with our colleagues.

Marvell Packaging Substrate team is a place where you can brainstorm, excel, innovate, transform for the expansion of AI-driven cloud data centers for a once-in-a-lifetime opportunity. As the substrate engineer, you will have the opportunity to work closely with world class substrate suppliers to execute and deliver cutting edge products. You will bring your expertise in optimizing ABF substrate manufacturing/process for solutions and will be responsible for developing advanced ABF substrate materials and technologies to support cutting edge package solutions in all product portfolios. 1. Drill on each substrate process to solve critical substrate technical problems and quality hiccups in NPIs and HVM products. 2. Benchmark, develop, implement new substrate materials into HVM to support advanced node cutting edge silicon products. 3. Define, fine tune, and optimize each ABF substrate manufacturing/process for advanced substrate technology including embedded substrate, MLC, and advanced substrate materials. 4. Be an expert to troubleshoot and support substrate issues on NPIs/HVM and new advanced technology. 5. Interface substrate suppliers and material suppliers to optimize manufacturing/process and control reliability & quality for NPIs and HVM products. 6. Drive NPI design review into timely manufacturing and substrate delivery. 7. Execute substrate cycle time, delivery commitment, substrate qualification & reliability tests. 8. Provide substrate milestones for NPIs into HVM products. 9. Establish the FMEA methodology and spec. 10. Manage substrate suppliers and OSAT substrate team for spec alignment such as substrate parameters & criteria, substrate tray design and selection. 11. Work closely with functional teams including NPI, Quality, Assembly, Test, and BU's. 12. Work with QA, OSAT/substrate suppliers to resolve package related quality/reliability issues.

• Responsible for system-level IP validation such as High-Speed SerDes, PLL, ADC, power regulator, temperature sensor, etc. • Responsible for support on SoC system solutions for PCIe, Ethernet, SATA. SAS and USB. • Responsible for instant troubleshooting and problem-solving for SoC issues using CE IPs. • Responsible for collaborating with chip-level IP validation and design teams for test coverage enhancements.

Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. ASIC design engineer responsible for post-RTL design flow. You will be responsible for block and /or chip-level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to: · Improve the design methodology and flow. · Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. · Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. · Provide support to the product teams, for both pre and post-silicon.

* Design, development and verification of new firmware features. * Participate in design reviews. * Deliver architectural documents, design specs, firmware source code and build scripts. * Perform tasks including debug, bring up, beta and production firmware development. * Collaborate with design, application, SoC team.

We are seeking a skilled and motivated Application Engineer to join our dynamic team. The ideal candidate will be responsible for designing, developing, and maintaining Baseboard Management Controller (BMC) software solutions for our products. This role involves close collaboration with hardware and software teams to ensure seamless integration and optimal performance. Key Responsibilities: 1. Design, develop, and maintain firmware and features in OpenBMC solutions. Perform code reviews, unit testing, and debugging to ensure high-quality and reliable OpenBMC-based software. 2. Develop and maintain documentation, including design specifications, user manuals, and release notes. 3. Collaborate with cross-functional teams to resolve complex technical issues.

As Marvell SQE, you will have the opportunity to work with world class Offshore Assembly and Test (OSAT) service providers to deliver leading edge products to the world. * Manage OSATs suppliers’ quality. * Collaborate with suppliers on Continuous Improvement Programs. * Oversee periodic quality reviews with suppliers (Yield, DPPM, CPK, ORM). * Conduct supplier audits and host customer audits. * Manage Supplier Process Change Notices. * Chair Material Review Board (MRB) and handle non-conformance material disposition. * Manage supplier/customer 8D SCAR, and implement corrective/preventive actions effectively. Work with Customer Quality Engineering (CQE) on customer requests.