About us: VICI Holdings' Hardware team is seeking a skilled Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities： • Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application • Develop high speed data paths, ensuring minimal logic depth and efficient pipeline • Optimize critical paths and combinational logic to reduce propagation delays and improve throughput • Work with Verilog/ System Verilog to implement RTL design • Apply parallelism and resource sharing techniques to enhance performance and throughput • Develop latency-aware micro-architectures for real-time processing and networking applications • Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation • Work closely with digital/system verification engineers to ensure functional correctness and performance validation 【FPGA Verification and debug】 • Take ownership of FPGA verification tasks to ensure design correctness and performance. • Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches. • Support system validation engineer to debug FPGA issue 【Tool Expertise】 • Utilize Altera/ Xilinx verification tools, including Quartus/ Vivado, to validate FPGA designs efficiently. -> is a plus • Resolve issues with system validation engineer, and ensure designs meet performance specifications. 【Design Collaboration】 • Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture Performance Analysis: • Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases. • Capability to solve routing timing issue and analysis FPGA timing report result 【Candidate Requirements】 • BS/MS degree above from EE, CE • Strong experience in digital circuit design, especially high-performance, low-latency application • Experience with low-latency datapath design, including mathematics, multiplexers, FIFOs and registers • Strong debugging and optimization skills using simulation tools (VCS & Verdi) •　 Experience using Quartus or Vivado to conduct FPGA verification • Experience in high-speed interface design or knowledge in PCIE/ Switch/Ethernet/MIPI/DDR implementation is a plus. • Familiar Linux/ Unix working environment • Experience with FPGA design and prototyping for fast iteration and validation • Strong debugging and optimization skills using simulation tools (VCS & Verdi) •　 Strong analytical and problem-solving skills, with an emphasis on performance-driven design Other Requirements: • Demonstrated ability to tackle complex design challenges and implement effective solutions. • Familiarity with high-bandwidth memory interface (DDR, HBM, etc.) • Exposure to networking protocols (Ethernet, PCIe, etc.) • High self-motivated individual with good communication skill • English level – working level proficiency is a plus. Interview Process: • HR Phone Interview(15-30mins) -> Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

This is a good opportunity to join a startup company working in UWB and Radar product. Co-work with ASIC design team for product development competive salary and startup package 工作內容: - 協助UWB定位演算法DSP實現及其驗證 - 協助數位晶片Serial介面(I2C/SPI)開發 - 協助產品驅動程式開發和相關測試 具備條件: - 具3年以上Digital IC design或FPGA開發相關經驗 - 熟悉RTL coding、simulation & synthesis流程及其開發工具使用 - 具C/C++ coding 和 debug 能力 - 能理解基礎數位運算原理如FIR IIR cordic佳

Mini / micro LED driver design A. Mixed mode function design B. Source OP / P-Gamma C. LDO, bandgap等類比電路 -待過Display Driver IC廠商的經驗 -做過Display Driver IC的開發設計, 擅長下面任一電路均可 1. Source Driver/Source OP 2. Mipi/LVDS 或其他的high speed interface(USIT / iSP…) 3. 或其他跟Display相關的電路經驗

1. Algorithm/Spec to RTL design, verification and synthesis 2. IP FPGA verification 3. Stardand IP configuration, integration and verification 4. Whole chip/Subsystem IP Integration and verification

1.計算BL length與parasitic capacitance 对 loading及couple effect的影響 2.建Array model及simulation 3.計算sense margin 4.具以下設計經驗者佳: (1). DRAM Array設計 (2). DRAM WL driver 及 Sub-WL driver (3). DRAM BG control設計，調WLon to SA timing, SA to WLoff timing, tRP/tRCD/tWR等 Array相關timing (4). WL decoder, WL redundancy (5). Sense amplifier (6). OCSA (offset cancelling sense amplifier)

Digital designer with knowledge of embedded micro SOC developments and capability of carry a design from concept to production. The candidate should be skilled with hardware description language, formal verification methodology, logic synthesis, and timing closure. Knowledge of back-end design and experience of work closely with physical designer to complete place & route and meet power & timing contains are highly desirable. Project management skill is a plus. The senior candidate with ARM design platform experience and familiar with 55/40 nm MCMM implementation design flow as well as PPA analysis is a big plus.