Position Description: The candidate will focus on Chip, IC Packaging, Board space and 3D-IC application development. The candidate will work with customers to deeply understand their requirements and discuss these with the factory to develop the required software. Preferred Qualifications: • Master's degree in Computer Science, Electrical Engineering, or a related field. • Experience in software performance, software capacity, software usability, or EDA software development. Position Requirements: • Programming language: Java (major), C/C++ (minor) • Common Skills: shell script, or Tcl script • Strong background in one of the following: - Database Optimization Development □ Focus Domain: Compiler, Computer Architecture, Database Theory, Virtual Machine. - Database Core Development □ Focus Domain: Database Theory, Information Theory, Information Security. - Design Rule Development □ Focus Domain: Computational Geometry, Linear Algebra, Calculus. - Software Quality Development □ Focus Domain: Software Testing, Compiler, Programming Language Design. - Data Processing Development □ Focus Domain: Parallel Programming, Compiler, User Interface Design, Computer Graphics. - EDA functionality development □ Focus Domain: Design Flow Automation, Software Integration • Knowledgeable in UNIX and Windows • Knowledgeable in Electronic Device Nomenclature • Ability to work individually or with a small distributed team • Ability to interact professionally with the customer • Ability to profile the values, requirements, issues, and risks. • Ability to communicate in English. *If you're interested in this role, please click link below to learn more about Integrity 3D-IC Platform. https://www.cadence.com/zh_TW/home/tools/digital-design-and-signoff/soc-implementation-and-floorplanning/integrity-3dic-platform.html

We are seeking a Application Engineer (Verification) to join our high-impact team focused on delivering comprehensive verification solutions tailored to customer needs. This role requires a strong background in digital verification methodologies, as well as the ability to understand customer design challenges and propose solutions using Cadence’s suite of verification tools, including Xcelium, Jasper, Verisium, and Verification IP (VIP). As a trusted technical advisor, you will engage with leading semiconductor companies to promote the adoption of Cadence’s verification technologies, ensuring successful deployment and long-term customer success. Responsibilities: • Engage with customers to understand verification challenges and provide customized solutions using Cadence verification platforms • Drive technical pre-sales activities, including evaluations, benchmarking, and solution positioning • Support post-sales adoption by helping customers integrate Xcelium, Jasper, Verisium, and VIPs into their verification flows • Deliver technical presentations, demos, and customized trainings • Collaborate with internal teams (R&D, PE, support) to align on customer requirements and provide timely issue resolution • Participate in knowledge sharing through events, collateral development, and best practice dissemination Qualifications: • BS/MS in Electrical Engineering, Computer Science, or related field • 5+ years of experience in digital design or functional verification (at SoC, IP, or subsystem level) • Knowledge of assertion-based verification and experience with tools such as Xcelium, Jasper, Verisium is a strong plus • Strong scripting skills (Python, TCL, shell scripting, etc.) • Excellent problem-solving and communication skills; ability to work collaboratively in multi-functional, multi-cultural environments Preferred: • Hands-on experience using Verification IP in UVM-based environments • Strong understanding of UVM and functional verification best practices • Understanding of CPU architecture and verification challenges • Knowledge of low power design techniques and associated verification flows (e.g. UPF) • Familiarity with one or more of the following protocols is a strong plus: AMBA (CHI, AXI, AHB), USB (2.0/3.x/4), LPDDR (3/4/5/6), UFS5, UniPro, MPHY, PCIe, DisplayPort, eMMC, HBM • Exposure to coverage-driven verification, debug automation, or formal verification

請務必上官網投遞履歷: https://careers.synopsys.com/job/hsinchu/nvm-device-engineer-sr-staff/44408/79348503936 Synopsys is seeking senior staff device engineer to join its growing NVM team. In this highly visible position, you will play a key role in implementing Synopsys NVM IP in multiple technologies with top semiconductor foundry partners. You will use your deep knowledge of semiconductor device physics to design and implement NVM bitcells. You will work with highly skilled and diverse engineers to build next generation NVM products leading to our future growth. What you'll do…. • Design and characterize NVM bit cells on a wide range of foundry processes. • Layout test structures to evaluate novel bit cell concepts. • Perform bench measurements to understand basic device characteristics and bit cell performance. • Setup and maintain a device lab. • Spice simulation to understand device behaviors, often outside the range recommended by foundries. Collect necessary bench data to support modeling. • Evaluate foundry PDK changes and provide expert advice to design team on their impacts to NVM design. • Understand ESD and latchup prevention techniques. Able to advice design and layout teams to achieve solid ESD and latchup protection. • Understand reliability checks like SOA, EMIR, Aging, PERC. Work with design and layout teams to fix (or justify waiving) the violations. • Work with different engineering teams with diverse disciplines across multiple geographic area and time-zones. • Review foundry electrical and reliability data to ensure successful implementation of Synopsys NVM IP. Work with foundry for additional device data collection if needed. Requirements: • MS in EE or related fields with at least 10 years of experience in semiconductor industry. • Solid knowledge of device physics and reliability. Experience in NVM is a plus. • Experience with bench measurement. • Good understanding of state-of-art process flows such as HKMG, FinFET, GAA and SOI. • Familiar with common EDA tools (such as Spice, layout, DRC, LVS, etc.) • Team player. Ability to lead, influence and corporate with other team members for common goals. • Multi-tasking skills managing multiple projects simultaneously without schedule slip. • Excellent people skill. Able to maintain smooth working relation with wide range of customers and partners, both internal and external. • Excellent written and oral communication skills. Able to conduct verbal and written communications in English. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Job Description: • EMX and Clarity certification • EMX and Clarity support for key customer • EMX and Sigrity Tool Simulation to Silicon correlation Position Requirements: • Master Degree required; EECS preferred • Good understanding of Python. Candidate must be experience in basic design skills to be able to work on automation and come up with technical solutions. • Must possess strong verbal and written communication skills • Ability to work independently • Good at analysis, debugging and troubleshooting issue • Experiences on Python/TCL/shell scripting for task automation is a plus. • Knowledge on Signal integrity and Power integrity is a plus • Knowledge on RF and Microwave circuits is a plus • Experiences on Cadence SI/PI/EM tools, such as Sigrity, EMX and Clarity is a plus.

Job Responsibilities: Develop, validate, and deploy 3D-IC system-level design planning & physical implementation flow. Design flow automation for 3D-IC system-level analysis & physical verification and verify simulation results. Work closely with cross-functional teams, project managers, and customers to explore, develop and drive 3D-IC implementation, RC extraction, analysis, and verification flow enablement. Job Requirements: Solid working knowledge and hands-on experience in synthesis, block, or top-level physical PnR implementation, and signoff flows. Strong programming and scripting skills in Tcl and Shell. BS or MS degree in EE, EECS, or CE with 5 years of engineering experience in the semiconductor industry. Excellent skills in problem-solving, written and verbal communication, excellent organization skills, and highly self-motivated. Independent, self-starter who can work across a worldwide organization and customer base.

This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D. You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow. You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes. You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach. You are an excellent communicator. Position Responsibilities: Support Cadence products in the Digital and Signoff team. Track and debug customer issues and work with R&D and release team on issue resolution. Run design benchmarks and develop flows and solutions. Position Requirements: BS in EE with 4+ year experience or MS in EE with 2+ years of experience in Digital Implementation, either as an AE, design engineer or as a product engineer Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff. Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes. Energetic team player with a passion for problem solving Strong analysis skills with a track record to prove it Strong communication skills (verbal and written) Automation skills using Perl, Tcl and shell scripting