負責Central Design Verification Methodology
1. Develop and maintain central DV methodology
2. Co-work with SBU's design team and DV team to evaluate new DV flow
3. Debug and analyze unit/block/wholechip verification environment
4. Technical consulting of various verification methodologies
【必要條件】
1. Hands-on experience on wholechip test bench build-up : IP and SOC level TBs
2. Hands-on experience on high-speed IO protocols verification, like PCIe, USB3, USB4, DDR4, LPDDR4。
3. Experiences in using commercial (e.g. Synopsys, Cadence) VIP
4. Familiar with verification methodology such as UVM, VMM, or OVM
5. Familiar with Verilog/SystemVerilog and script language
【共創A+聯詠】
穩健踏實、專家精神、創造優勢
驅動科技、開發創新、引領未來
邀請優秀人才,共創A+聯詠