• Use Voltus to check IR drop. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/

development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the

Job Contents · 3+ years of EDA flow expertise. · Responsible for timing closure / signoff flow development including timing

The role could be: - Develop implementation/signoff flow for the latest design process in Novatek. - Evaluate/Develop new

place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues,

1.Familiar with IR signoff tool Voltus/RedHawk for IR hot spot diagnosis/EM analysis) 2.Familiar with Innovus is plus 3.

Position Description: 1. To provide key technical support in digital IC design signoff product (Tempus/TempusECO/Certus)

Fixing (PT) 5.IR-Drop/EM Analysis and Signoff (RH) 6.Low-Power, Multi-Voltage Low-Power Implementation (UPF) 7.PV Signoff:

[駐點於知名科技公司服務] 希望你對最新科技技術和EDA工具有強烈的學習熱情，並且願意參與從SYN、APR、signoff到Foundation IP最新技術的開發，將這些技術應用到最前沿的產品中。 1. 設計流程維護： 維護和優化CAD參考

achieve best Power/Performance/Area Goals. Synopsys’ PrimeTime & Signoff tool is an advanced transistor-level static timing

(1) SDC validation and perform STA (2) Advance STA signoff flow, domain knowledge enhancement (3) Timing closure with APR

coverage closure Clear mindset on how to achieve DV quality signoff Good communication skills in English and Mandarin to

Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip

specification validation and in-house development if needed - UAT preparation, co-ordination and user signoff - Manage application

signoff • Familiar with 3D/2.5D/2D electromagnetics and spice simulation tools • Excellent oral and written communication skills

place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow

and digital IC design flow, including RTL sign-off, Synthesis, LEC, STA, timing-signoff. 2.Better to have DFT/ATPG and MBIST

and digital IC design flow, including RTL sign-off, Synthesis, LEC, STA, timing-signoff. 2.Better to have DFT/ATPG and MBIST

12nm, 7/5nm Automotive process及其Signoff Criteria. 2. 晶片布局設計：根據Design Specification, Pin Table, Netlist，執行Floorplan規劃及設計。 3. 熟悉

that you could also expand your technical skills from P&R to Synthesis and Signoff. Does this sound like a good role for you?