1. Responsible for SOC physical implementation including floorplan, power plan, physical synthesis, clock tree, routing, RC, STA, timing closure, EM/IR, DRC/LVS to GDS out. 2. Responsible for APR physical design flow development & automation

1.負責 Digital IC 設計流程開發及驗證 2.CAD design environment automation and Modeling 3.APR physical design methodology development & automation

1. Deal with all aspects from gate level netlist to GDS. 2. Implementation with emphasis on floorplan, clock tree synthesis, place and route, STA, power analysis. 3. Sign-off verification of block/whole chip level physical implementation with QoR (power/performance/area) consideration. 4. Checking and fixing of DRC, LVS. Antenna.

ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication

Innovus or Synopsys ICC2/Fusion Compiler. 2. JLPT N2 up is preferred. 3. TOEIC 730 up is preferred.

tapeout. 職缺需求: 1.Familiar with Synopsys (ICC2 or FC & PrimeTime)/Cadence (Innovus & Tempus) 2.Perform netlist-to-GDSII design

Cadence Innovus & Synopsys ICC/ICC2 experience is required

1. VLSI Advance Technology Node (2nm and Below) Physical Design Implementation. 2. Comprehensive scope to touch, including chip floorplanning, a variety of design closures on timing, signal integrity, power integrity, DFM as well as physical verifications. 3. Develop physical design flows/solutions on the cutting edge technology node.

1. Responsible for test chip physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking. 3. Working on advanced process node design methodology, PD execution and sign-off

1. SOC physical design implementation including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout etc. 2. Build physical design implementation flow for advanced process nodes including timing/power/DFM closure and CPU/GPU hardening. 3. Project leader and cross team project handling 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠

Back-End IC Implementation & Verification based on Synopsys/Mentor Tools: 1.Chip/Block Floorplan/Powerplan (ICC2) 2.Place &

of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk) - Experience in Clock/Power

Responsible for physical verification，including DRC、LVS and IR drop analysis。 3、熟悉操作Cadence Innovus or Synopsys ICC/ICC2等Tools。

on whole chip APR physical design from netlist to DRC/LVS tapeout - Familiar with Cadence Innovus & Synopsys ICC/ICC2

1. SOC physical design implementation including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠

1.Responsible for ASIC Backend / Physical Implementation including floorplan, power plan, placement, clock tree synthesis, routing, timing analysis. 2. Responsible for physical verification, including DRC, LVS, IR drop analysis.

1. Responsible for test chip physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking. 3. Working on advanced process node design methodology, PD execution and sign-off

deep understanding of physical design methodologies, including ICC2/FC or equivalent physical implementation tools. You have

Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.

Familiar with Cadence Innovus & Synopsys ICC/ICC2 experience is required