1. Block level & Top level APR implement. 2. Including Library preparation, floorplan, power plan, CTS, timing closure, PV

1. Perform Netlist-to-GDS design flow, (TSMC 16 – 5 nm) -- including floorplan, placement optimization, clock tree synthesis and routing -- Low power layout with UPF, including multi-vdd, voltage island layout 2. Support STA timing analysis and ECO fixing 3. Perform physical verification, including DRC, LVS, Antenna check 4. Perform PG layout verification , including IR drop & EM analysis

1.負責 Digital IC 設計流程開發及驗證 2.CAD design environment automation and Modeling 3.APR physical design methodology development &

【職務說明】 Familiar with APR (ICC) flow from floorplan , power plan , placement , cts , routing , timing analysis and fixed ,

1. VLSI Advance Technology Node (2nm and Below) Physical Design Implementation. 2. Comprehensive scope to touch, including chip floorplanning, a variety of design closures on timing, signal integrity, power integrity, DFM as well as physical verifications. 3. Develop physical design flows/solutions on the cutting edge technology node.

1. APR physical design: floorplan, power plan,physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR

1. Responsible for test chip physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking. 3. Working on advanced process node design methodology, PD execution and sign-off

1. 負責後段APR flow 　 Familiar Netlist-to-GDS Design flow. Including,Floorplan/Power Plan/IR drop analysis、Placement/CTS/

1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2. Responsible for Physical Design flow research, development and automation.

Job Summary: The Staff Physical Digital Design Engineer will be responsible for all aspects of physical design and implementation. In this role, you will participate in the efforts of establishing physical design methodologies and flow automation. The candidate will work on the digital design implementation, and verification of mixed-signal ICs utilizing standard EDA tools. Products to be designed/verified include power management and mixed signal functions. Products: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital camera, automobile and network equipment. Essential Functions: • Responsible for physical design, development, & verification of digital / mixed-signal IC's • Chip & block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, & LVS/DRC to closure • Work closely with digital/analog design team for physical implementation and custom analog blocks/interface/IP's • Help build an automated environment for RTL-to-PNR using high level languages and devops-like services Qualifications: • MS/BS in Electrical Engineering or equivalent. • 8-10 years or above experience of Physical Digital Design experience. • Strong knowledge of ASIC development process and digital design techniques. • Strong technical abilities & understanding in these areas: 1. Synthesis, LEC, CTS, DFT, RC Extraction, and STA closure across multiple process corners. 2. Multi-power domain, signal integrity, & power/IR drop analysis. 3. Expertise in both hand-written and tool-driven functional/timing ECO. 4. Physical Design Verification methodology to debug LVS/DRC issues at chip/block level. 5. Industry physical tools: Cadence (preferred) or Synopsys. • Experience with the following is desired: 1. Knowledge of power management industry/applications 2. I/F: I2C, I3C, SPI, USB, PMBUS, etc 3. Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression, MBIST etc. 4. Project leader and cross team communications experience is a plus. • Good written/verbal communication English skills and strong teamwork collaboration • Ability to lead project, optimize the implementation, and execute tasks to hit milestones with quality. • Experience with programming, scripting and automation languages like Perl/Python/TCL/Unix

1. Familiar with Virtuoso Calibre tool, DRC and LVS command files (熟練 APR tool) 2. Can perform Power/Ground layout

(1)Analog and Digital IC Layout或具APR經驗者。 (2)熟悉Laker Tool與Calibre verificaiton Tool等工具軟體使用。

APR Engineer : 1) Block level & Whole chip Physical Implementation. 2) Including Library preparation, floorplan, power plan

Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.

methodologies and execution • Requirement: - Hands on whole chip APR physical design from netlist to DRC/LVS tapeout -

1.IC fully layout 2.類比 IC Layout 經驗者佳或具APR經驗者。 3.具Tape out 量產經驗，能獨立處理Whole Chip者優先考慮 4.熟悉layout tool或verification tool等工

APR Physical design ( P&R ), including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to

Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.

1.IC fully layout 2.類比 IC Layout 經驗者佳或具APR經驗者。 3.具Tape out 量產經驗，能獨立處理Whole Chip者優先考慮 4.熟悉layout tool或verification tool等工

具Analog and Digital IC Layout 三年以上經驗者，有APR經驗者尤佳。 (2)熟Virtuoso 、Laker 、Calibre操作。