一、RFQ/RFI process 二、BOM cost control 三、PCB/FPC打樣承認導入 四、PCB/FPC 詢價、比價、議價 五、採購策略擬定、執行、管理

* 評估開發專案可行性, 適用之 solution * 轉量產前客戶與RD內部的時程規劃、控管、跟催 * 控管專案成本, 品質 及 風險管理 * 與客戶及供應商之間的聯繫 * Hapticpad solution、指紋辨識 solution 及 其他創新專案開發 * 成員管理

誠徵各科AP (Advanced Placement) 家教/團班老師 1. Physics 1,2,C 物理 2. Computer Science 電腦科學 3. Statistics 統計學 4. Environmental

1. 個人電腦、週邊設備及網路設施之軟硬體維護、問題排除及安裝設定。 2. 網路連線問題排查。 3. 提供客戶資訊系統技術咨詢及使用疑難諮詢解答。 4. 協助處理設備維修、送修事宜相關工作。 5. 協助處理業務資料表單整理及彙整

1.針對客戶環境及需求，分析資訊安全弱點並導入資安解決方案 2.根據客戶需求，提供專業的諮詢服務並制定資安管理規則 3.進行系統與網路日誌分析與追蹤，持續提供監控服務 4.進行資安事件分析，評估異常登入、惡意程式、列舉攻擊等事件，並建議客戶進一步的處理措施 5.熟 Fortinet FortiGate、FortiAnalyzer 等操作運用 6.協助提供售後技術諮詢、障礙支援 7.撰寫專案文件與技術文件說明，提供客戶教育訓練 8.與原廠工程師協同合作處理技術問題 9.對MITRE ATT&CK 框架具備一定概念 10.依據客戶需求，固定每月制訂資安會議簡報 資訊安全是現今社會不可或缺的一環，而資安工程師則是保障資訊安全的重要角色。在這個日新月異的科技時代，資安工程師職位的需求量也隨之增加，且具有良好的發展前景。 如果您符合上述條件，並渴望成為資安領域的專業人士，歡迎申請我們的職缺!

業務及行政之助理工作 熟悉Microsoft Office文書相關軟體操作 協助資訊及相關資料檔案管理作業、一般行政庶務工作 及機關臨時交辦事項 抗壓性高，主動積極、良好溝通、團隊合作 歡迎 所有求職者 原住民 應屆畢業生 夜間就學中 …等

供資訊安全事件及回應的專業諮詢服務。 6. 提交評估報告及簡報。 7. 監控安全服務品質並處理客戶詢問。 8. 根據指定要求處理臨時項目。 工作要求 1. 具網路安全、資訊科技、電腦科學或相關專業大學以上學歷。 2. 2年以上資訊安全相關工作經驗

1.各機型檢測維修 2.故障率報表分析 3.測試新機型功能 4.測試備品 5.機器整理及包裝 6.定時往返收送維修機 7.協助出貨 8.主管交辦事項 9.具相關維修經驗者尤佳

品開發。 【職務需求】 - 資訊相關科系：資訊工程、電腦科學等資訊相關科系或同等專業經驗。 - 具有網絡原理和故障排除的基本理解或實務經驗。 - 具有Linux操作、設置的基本理解或實務經驗。 - 對技術充滿熱情，並按照指示學習新技術領域。

Job Description 1. Assist in Cadence Genus/Innovus/Tempus (Back-End & signoff Design Tool) development and validation; 2. Develop testsuites to ensure the good STA quality, ensure the correctness of timing analysis in each stage of the digital implantation flow 3. Assist in Cadence Innovus RC extraction verification for advanced nodes Additional Job Description 1. The candidate should be familiar with Linux system, and proficient scripting skills with TCL/PERL/Shell/Python; 2. The candidate should have MS degree, or bachelor degree with 3+ years of digital design experience; 3. The candidate should be familiar with digital circuit design implementation flow, STA/Extraction knowledge is a preference; 4. Good team player with strong written and verbal communication skills, and with good patience & responsibility.

1. 資訊機房伺服器管理。 2. 機房維運設備檢查、備份作業檢查、例行維護。 3. 基礎網路營運除錯，熟悉網路設備設定及架構優化調整。 4. 規劃網路管理機制，建立及改善標準作業流程。 5. 其他主管交辦事項。 【加分項目-任一皆可】 1. 具備資訊領域相關證照者為佳，如CCNA 2. 熟悉網路架構維護，如防火牆(Firewall)、路由器(Router)、交換器(Switch) 歡迎 所有求職者

保 AI 解決方案的安全性、可擴展性與效能。 - 研究工作，探索並整合尖端的 AI 技術。 職位要求： - 擁有電腦科學、人工智慧或相關領域的學士、碩士或博士學位。 - 具備 AI 工程師或資料科學家的經驗，並有成功主導 AI 專案的實績。 -

密外洩以及員工不當使用電腦 4.用者電腦故障排除,軟體安裝、設定、系統操作，與分析網路資料傳輸與網路安全架構等特性，以設計、發展及維護網際網路系統之正常運作 5.對網路安全系統之運作、管理及周邊設備之採購作業，提供技術性建議 6.安裝、

保 AI 解決方案的安全性、可擴展性與效能。 - 研究工作，探索並整合尖端的 AI 技術。 職位要求： - 擁有電腦科學、人工智慧或相關領域的學士、碩士或博士學位。 - 具備 AI 工程師或資料科學家的經驗，並有成功主導 AI 專案的實績。 -

Job Description: This position is in Cadence Pegasus Physical Verification R&D team in Hsinchu, Taiwan. The candidate for this position will be developing design rule check (DRC) and FILL decks for advanced nodes of semiconductor manufacturing, The job involves creating quality check (QC) patterns, writing physical verification DRC and FILL rules and developing decks consisting of these rules. It also involves testing these decks on real customer designs and troubleshooting the deck and tool issues, providing feedback to Pegasus Foundry Team, Pegasus R&D, and foundry partners. Requirement: At least 2 years of previous experience with DRC or FILL deck development, and BS or MS degree in engineering.

於專案中。 - 透過先進的分析與視覺化技術，推動以數據為基礎的決策。 - 確保 AI 解決方案的安全性、可擴展性與效能。 - 主導研究工作，探索並整合尖端的 AI 技術。 職位要求： - 擁有電腦科學、人工智慧或相關領域的學士、碩士或博士學位。

、NP問題和軟體開發有高度熱忱，又想做世界級題目的，一定要丟履歷過來！ 奇點無限的AI Routing在日前的美國離散數學與理論電腦科學中心(DIMACS)舉辦的VRP挑戰賽擊敗Google AI團隊與日本黑貓宅急便團隊，目前世界排名第9。

We are looking for Formal Verification Application Engineer who will join a highly motivated team and will be responsible to enable semiconductors companies adopting Cadence Jasper Formal Verification Platform and associated methodologies Job responsibilities: • Prepare and drive Pre-Sales engagements to introduce and proliferate the Cadence verification solutions • Integrate Cadence solutions into the customers environment • Assist customers to become experts with the Cadence technologies • Analyze technical problems and find solutions • Deliver dedicated trainings • Prepare and drive customer events Required Qualifications: • MS in Electrical Engineering, Computer Science or relevant discipline is required • Design/Verification experience as part of a SoC/CPU/IP development team • Have a basic understanding and experience with formal verification techniques • Have basic experience in assertion languages (e.g. SVA, PSL) • Have a strong motivation to quickly learn state-of-the-art Cadence functional verification tools, flow and methodologies • Master effective communication skills in a multi-cultural and cross-functional working environment Following technical skills or experience would be considered as differentiating: • Years of formal property verification experience using industry tools such as Jasper, Questa Formal or VC Formal. • Experience on SoC chip design/integration • Experience on multi clock domain design/verification • Experience on UPF low power design/verification • Knowledge of typical standard protocols (e.g. AMBA AHB, APB, AXI) • Scripting languages (e.g. TCL, Python, Perl, UNIX-Shell)

The Virtuoso team is seeking a Product Engineer to help drive the industry’s leading analog design automation tool. The Product Engineer (PE) bridges the gap between customers, R&D, and field Application Engineers (AEs). In this highly creative and innovative role, they are responsible for ensuring that existing flows meet the ongoing needs of our customers, while also developing flows and requirements to solve analog design automation challenges. The PE will collaborate closely with both customers and R&D to drive specification, implementation, and evaluation/benchmarking of the new solutions. In addition, the PE will be responsible for the roll-out of new features to AEs and customers, and in some cases will play a pivotal role performing hands on work, (remote or onsite) to enable key customers to achieve deployment. This position gives abundant exposure to work on and influence the latest design styles and methodologies that are used by semiconductor companies. This job may occasionally involve worldwide travel to attend meetings or conferences, or to assist with product demonstrations and evaluations at customer sites. The candidate must have clear understanding of analog design and have hands on experience in layout design on advance nodes. Scripting knowledge is added advantage

The Cadence Protium team is looking for talented software engneer to join and contribute to our Protium compiler router development. You’ll have a great opportunity to make a difference by applying your engineering and team collaboration skills to optimize the compiler for compile time, fclk performance and memory efficiency. Requirements · MS with 3+ years or PhD with 2+ years in engineering, computer science or related field. · Strong understanding of data structures, algorithms and databases. · Demonstrated proficiency in C++, gdb debugging, and general software development skills

Position Description -Responsible for the development of Pegasus, our next-generation massively parallel physical verification system, with focus on the Fill and DRC product development and foundry enablement. -Performs as individual contributor on case analysis, problem solving, validation and documentation. -Working closely with PE and QPV for the DRC/FILL deck developing and QC pattern generation. Requirements -Solid background in computational geometry and graph algorithm. -Excellent programming skill in C/C++/Python. -Some knowledge on the foundry qualification of EDA tool is preferred. -Good English reading and writing skills. -Good communication skills.

Job Description: As a Verification IP Engineer for RSS Verification IP team, you will be expected or tanning to be an expert in a specific domain of Verification IP family- protocol and product-wise. The Application Engineer main role is to help accelerate VIP portfolio adoption at Cadence’s customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a VIP and protocol expert, the Application Engineer drives product knowledge transfer to customer, providing training and requirements collaterals. The Application Engineer is expected to collaborate with other team members (R&D, PE and support) to ensure the design is in line with the technical and quality requirements set for the customer’s requirement. Requirements and Qualifications: • BS/MS with Electrical engineering or Computer Science. • At least 3-5 years of experience with Verification or Design Experience. • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. • UVM based functional verification environment development is required. • Familiar with anyone kind of standard protocol is desirable. • Team orientation, mature work attitude, and good judgment under pressure. • Position requirements, propose solution, evaluate prototype flow and drive to success • Plan, execute and manage key technical evaluations and benchmarking • Conduct basic and advanced trainings, presentations and demos as necessary