【工作內容】
1.感測LED晶片開發
2.新產品設計開發驗證並協助導入量產
3.與工程、磊晶、品質單位合作確保開發流程順利
4.LED製程優化提升產品特性
5.規劃DOE實驗
6.新材料&新化學品評估
7.撰寫專利内容
8.產品失效分析
1. Responsible for developing sensing applilcation LED chips
2. New product introduction from design stage, verification stage and integration for mass production
3. Cooperate with process engineering, epitaxial team and quality team during product deveopment phase
4. Opimization LED process to improve performance
5. Carry out DOE experiments
6. New materials or chemicals evaluations
7. Patent cliam drafting
8. Failure anlaysis
1. 採用CMOS、SOI技術或是III-V GaAs製程進行混合訊號、類比電路和RF射頻電路的電路佈局。
2. 溝通能力佳,能與電路設計工程師一起進行晶片布局檢視和分析。
3. 能配合不同電路設計團隊規劃及安排工作時程,必要時針對佈局工作做出相關的權衡。
4. 解釋LVS、DRC和ERC報告,並和電路設計工程師討論完成佈局的最佳方法。
• Designing complex layout for mixed signal, analog and RF circuits in deep sub-micron CMOS technologies and / or III-V processes.
• Reviewing and analyzing floorplans and complex circuits with circuit design engineers.
• Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed.
• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
1. 採用CMOS、SOI技術或是III-V GaAs製程進行混合訊號、類比電路和RF射頻電路的電路佈局。
2. 溝通能力佳,能與電路設計工程師一起進行晶片布局檢視和分析。
3. 能配合不同電路設計團隊規劃及安排工作時程,必要時針對佈局工作做出相關的權衡。
4. 解釋LVS、DRC和ERC報告,並和電路設計工程師討論完成佈局的最佳方法。
• Designing complex layout for mixed signal, analog and RF circuits in deep sub-micron CMOS technologies and / or III-V processes.
• Reviewing and analyzing floorplans and complex circuits with circuit design engineers.
• Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed.
• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
1. Manage the in-house failure analysis team and the failure analysis lab
2. Facilitate and lead failure analysis activities as part of the reliability engineering team for incidents originating from reliability testing for new product development
3. Create a knowledge management system to capture all failure analyses performed and assure that they can be easily retrievable
4. Own the roadmap for failure analysis equipment purchases in order to continue building internal capability
5. Lead the creation of failure analysis reports with exceptional visualizations and direct the communication and presentation of findings to project teams
6. Hands-on SEM/FIB and/or TEM experience
7. Knowledge and experience in semiconductor IC/laser/VCSEL processing technology