* 評估開發專案可行性, 適用之 solution * 轉量產前客戶與RD內部的時程規劃、控管、跟催 * 控管專案成本, 品質 及 風險管理 * 與客戶及供應商之間的聯繫 * Hapticpad solution、指紋辨識 solution 及 其他創新專案開發 * 成員管理

1.ERP系統管理及負責業務後段相關運作流程 2.協助業務人員處理銷售相關作業, 包括內/外銷之訂單處理, 內/外銷出貨安排, 發票, 對帳收款, 費用處理, 折讓…等作業、出口報關、物流安排等 3.支援內部定期與不定期之產銷相關會議之執行與協調 4.依照業務部門需求, 提供有利業務掌握庫存與銷售狀況之管理報表 5.協助內部文件整理,建檔與追蹤 6.其他業務主管交辦事項與業務部門後勤支援工作

1. SoC top-level (Analog+Digital) Integration 2. Design block integration, synthesis, verification

1. 撰寫及準備專利申請文件(中英文)。 2. 與客戶研發團隊溝通，理解發明保護重點並依此撰寫說明書文件。 3. 處理專利申請/答辯業務。 1. Draft and prepare patent application documents （in Chinese and English）. 2. Communicate with the client's R&D team to understand the key points of invention protection and draft the specification documents accordingly. 3. Handle patent application/response matters.

1. Analog LSI電路設計、Analog LSI Layout 設計 2. 數位LSI邏輯設計、數位LSI物理設計、LSI Implementation 3. LSI 測試、LSI電路板驗證

Chip level ESD design & analysis.

The EDA Application Engineer (EDA AE) is expected to support the sale and adoption of EDA products, assisting customers in achieving success with our Verification and Implementation related products, including System Level Design, Simulation, Synthesis, Test, Design Reuse, Place & Route, and more. Responsibilities include providing pre-sales activities and post-sales technical support such as technical presentations, technical support, product application, product deployment, expert training, and competitive benchmark. You should be able to serve as the product expert and drive the success of EDA design flow and tools. EDA應用工程師（EDA Application Engineer）的職責是支援EDA產品的銷售和採用，協助客戶在我們的驗證和實現相關產品上取得成功，包括系統層級設計、模擬、綜合、測試、設計重用、佈局佈線等等。職責包括提供前期銷售支援和售後技術支援，像是技術簡報、技術支援、產品應用、產品導入、專業培訓以及競爭性評估。您必須成為產品專家，引領EDA設計流程和工具的成功。 In addition, you will have the opportunity to work with and gain exposure to various designs while providing support to different customers. Through customer interactions, you can enhance not only your technical knowledge but also your soft skills, paving the way for a more diverse and successful career growth. 除此之外，您將有機會透過支援不同的客戶，接觸各種不同的設計。在與客戶溝通的過程中，您可以加強不僅是技術知識，還包括軟實力知識，為更多元的未來職涯發展打下基礎。 Key Qualifications  MSEE/BSEE or equivalent required, with 2+ years of experience  Experience in using ASIC/SoC front-end and/or back-end EDA tools with design knowledge is preferred  Strong customer sensitivity and ability to handle multiple issues while setting priorities  Demonstrates a helpful and caring attitude towards customers, with a desire to help them leverage new technologies  Self-motivated, capable of working independently, and possesses excellent communication skills, including a good command of English 主要資格：  具備碩士學位（MSEE/BSEE）或相當程度，並擁有2年以上的相關經驗  具有使用IC/ASIC/SoC前端和/或後端EDA工具的經驗，具備設計知識更佳  具有對客戶的敏銳觀察力，能夠處理多個問題並優先排序  展現樂於幫助和關懷客戶的態度，並渴望協助他們採用新技術  自我激勵，能夠獨立工作，具有出色的溝通能力，包括良好的英語掌握能力

1. 光學感測器相關IC的設計開發，可獨立完成IC的系統級架構設計，數位類比混合模擬驗證，Layout方案制定驗收。 2. 熟悉光學感測器常見的電路基礎模塊，依據系統需求對其噪聲/功耗等關鍵性能進行設計優化。 3. 熟悉半導體元件特性與

1. 主要著重於混和電路板(Analog + Digital)電路設計開發與佈局(layout) 2. 有MCU開發經驗者佳 3. 有FPGA、ADC、DAC整合經驗者佳 4. 有EMC解決經驗者佳 5. 協助返修產品檢驗 6. 其他主管交辦事項

1.邏輯電路設計與模擬 2.FPGA實作 3.電路合成

▋ 關於德州儀器 德州儀器(TI)是位居類比晶片世界領導地位的半導體設計與製造公司，持續提供創新及頂尖的半導體技術與產品，協助客戶開發最先進的電子產品。除此之外，TI也針對在校學生及初入社會新鮮人設計完整的培訓制度與挑戰性的工作內容，並提供具競爭

Do you expect to learn more the complete methodologies/solutions of design, implementation and analysis for a high-performance, power-efficient and area-effective chip developments? Do you also expect to explore the AI-driven solutions to accelerate chip design and improve efficiency throughout the design flow with AI-powered EDA tools? As part of our teams, you’ll have an opportunity to accordingly study, explore and design next-generation methodologies/solutions as follows. (1) Develop, maintain and optimize advanced methodologies for Frontend, Backend and Mixed-signal Design and implementation flows with the integrations of many corresponding EDA tools (Synopsys/Cadence/Siemens/Xilinx, ..., etc.) (2) Study, Explore and evaluate AI-driven design and implementation methodologies Currently, we expected this candidate is familiar with or interested in the related skill developments as follows. (1) Analog design flow and methodologies (Speed-up/Optimized simulation, mixed-signal co-simulation, EM/IR, Reliability Analysis, …, etc.). Knowledge of digital design flow using EDA tools (Synopsys, Cadence, Siemens (Mentor), …, etc.) is a plus (2) Programming/Scripting language like Perl, TCL, Python, C/C++, PERC, ..., etc. for flow automation (3) Be able to individually study and implement feasible solutions to resolve technical issues occurring in design and implementation flows. In our department, through kinds of flow developments and the related technical issue resolving, the following skill sets will finally be captured. (1) Extensive tool knowledge and experience for many different kinds of EDA tools and flow integration (Synopsys/Cadence/Siemens/Xilinx, …, etc.) used for Analog/Digital/FPGA Design and prototyping (2) Work with analog/digital design teams to coordinate a complicate project including Analog/Digital Designs for successfully tape out (3) Extensive AI-driven Analog/Digital/System Design and implementation flow We believe this position can be a great opportunity to extend your cross-fields IC design capabilities to include Analog, Digital and even System level designs for handling more complicate SoC design in the future.

Design High speed interface IC.

升產品效能！ 不只是畫線，更是讓每個電子元件精準到位！透過巧妙的PCB佈局設計，確保訊號穩定、降低干擾，讓產品發揮最佳性能。發揮你的專業，讓設計更上一層樓！ 3️⃣ 數位/類比電路設計｜精通電路，打造未來科技！ 在數位與類比電路設計領域發揮專長，

Design analog circuits and mixed signal IC.

1. SoC/AI晶片設計與測試 2. FPGA驗證系統開發 3. 類比IC設計

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dedicated and experienced Standard Cell Library Design Engineer with a passion for cutting-edge technology and innovation. You possess a strong background in designing and optimizing standard cell circuits, including flip-flops, clock gating cells, level shifters, power gating cells, and other complex circuits in advanced technology nodes. Your expertise in circuit design, layout design, and spice simulations allows you to excel in creating high-performance, power-efficient circuits. You thrive in collaborative environments, working effectively with geographically distributed teams and engaging in cross-functional collaborations to optimize designs across the entire design chain. Your strong analytical and logical skills, combined with your ability to mentor and coach junior engineers, make you an invaluable asset to any team. With a clear understanding of CMOS device characteristics, submicron process issues, and FINFET technologies, you are well-equipped to tackle the challenges of advanced technology nodes. Your scripting capabilities in TCL, PERL, and Python further enhance your ability to optimize and automate design processes. What You’ll Be Doing: Designing and optimizing standard cell circuits such as flip-flops, clock gating cells, level shifters, power gating cells, and other complex circuits in advanced technology nodes. Engaging in cross-functional collaborations for optimization across the entire design chain. Working closely with geographically distributed teams to achieve design PPA targets. Mentoring and coaching junior engineers to expand their skills. Conducting hands-on development and layout design. Running high sigma variation analysis in smaller technology nodes. The Impact You Will Have: Contributing to the development of high-performance, power-efficient circuits that drive the next generation of technology. Enhancing the performance, power, and area (PPA) of standard cell libraries. Facilitating cross-functional collaborations to optimize designs across the entire design chain. Mentoring and developing the next generation of engineers. Ensuring the success of projects through effective communication and collaboration with geographically distributed teams. Driving innovation in advanced technology nodes and submicron processes. What You’ll Need: Bachelors or MSEE or equivalent from reputed universities. 5+ years of Standard Cell library design & layout experience. Hands-on experience in Circuit Design, Layout Design & spice simulations. Experience in designing flip-flops, clock gating cells, level shifters, power gating cells, and other complex circuits. Familiarity with advanced technology nodes (16nm, 7nm, 6nm, 5nm, 4nm, 3nm, 2nm). Clear understanding of CMOS device characteristics and design rules in submicron process nodes. Scripting capability in TCL/PERL/Python. Who You Are: Strong analytical and logical skills. Effective communicator with the ability to articulate ideas and requests clearly. Collaborative team player who thrives in cross-functional environments. Mentor and coach who supports the development of junior engineers. Innovative thinker with a passion for cutting-edge technology.

1.撰寫各種微處理韌體程式。 2.硬體電路設計與維修。 3.專案開發與測試。

Verilog、RTL、FPGA、Design flow、analog、ASIC design flow、類比IC電路設計 具備高速傳輸PHY 的數位或類比電路開發 For SOC, automoive product

1. 各電腦週邊界面產品設計。 2. 類比及數位影像介面應用（VGA / DVI / HDMI / DP / MHL）。 3. 產品規格及系統設計規劃（LCD KVM）。 4. 產品電源及訊號量測。 5. 生產問題技術分析與協助。

1. 負責光電半導體晶片開發藍圖規劃及管理 2. 負責新晶片的開發和進度管理 3. 建立晶片技術平台和管理 4. 協同客戶開發晶片需求技術 5. 提供晶片技術解決方案

此職位相當重視技術性溝通的能力 1. 擔任公司內部與客戶之間溝通協調的窗口，並支援技術性開發。 2. 執行電路的設計與開發 3. 電路設計提案 4. 協助與公司的海外合作夥伴(特別是台灣) 進行設計業務方面的溝通與協調