「數位IC設計資深工程師」的相似工作

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責基礎元件 IP（Foundation IP）開發相關的Memory Designer RD職缺。 【將負責的工作內容】 1. SRAM circuit design 2. Memory compiler development 3. Memory instances characterization 4. Supervision of layout implementation 【條件與特質】 1. Be familiar with memory circuit design : full-custom, read/write operation scheme, sense-Amplifier analysis, RAM cell analysis, monte carlo simulation, read/write margin check. 2. Be familiar with tool : linux, spice, finesim, virtuoso, laker. 3. Experience with FinFET process or high sigma design will be better. 4. 5年以上相關經驗 5. 電機電子相關學系碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

1. 負責影像處理IP設計，與演算法工程師合作，將演算法以High Level Synthesis實作成數位電路 2. FPGA Verification

若有興趣者，請務必上傳英文履歷至官網,否則不予受理(職缺代碼9739): https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-staff-engineer-zebu/44408/78181675440 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly skilled engineer with a deep understanding of simulation, emulation, and compiler technologies. You bring extensive experience with HDL languages like Verilog and have previously worked with VCS and ZeBu platforms. Your proficiency in programming languages such as C/C++ is complemented by a strong grasp of data structures and algorithms, including graph theory. You excel in designing modular, scalable software architectures and optimizing software performance through multi-threading and operating system concepts. Your familiarity with version control systems like Perforce and Git enables you to manage code efficiently and collaborate seamlessly with other teams. You are an effective communicator, able to convey complex technical concepts clearly and work collaboratively in a dynamic environment. Your passion for technology drives you to stay updated with industry trends, and you actively mentor and guide junior engineers, fostering a culture of continuous learning and innovation. What You’ll Be Doing: 1.Designing and developing high-performance software for Synopsys' simulation and emulation platforms, including VCS and ZeBu. 2.Collaborating with cross-functional teams to enhance product capabilities and performance. 3.Conducting comprehensive research and analysis to address complex engineering challenges. 4.Leading project initiatives, ensuring timely and high-quality deliverables. Mentoring junior engineers and fostering a culture of continuous learning and innovation. 5.Integrating new technologies and staying abreast of industry trends to drive continuous improvement. The Impact You Will Have: 1.Enhancing the performance and reliability of emulation platforms used for cutting-edge silicon chips. 2.Driving the development of next-generation simulation and emulation tools. 3.Improving the usability and adoption of Synopsys products across various industries. 4.Contributing to a collaborative and innovative engineering culture within the team. 5.Advancing the future of technology and connectivity through continuous innovation. 6.Delivering high-quality, performance-optimized software solutions that elevate Synopsys' success. What You’ll Need: *CS or EE master's degree or above at least five of relevant experience. *Proficiency in programming languages: C/C++. *Strong understanding of data structures and algorithms, including graph theory. *Experience with hardware description languages like Verilog and scripting languages like TCL. *Prior experience with HDL simulation and emulation platforms, including VCS and ZeBu. *Familiarity with version control systems like Perforce and Git. *Ability to design and implement modular, scalable software architecture. *Proficiency in multi-threading and operating system concepts for software *performance optimization. Who You Are: A proactive and innovative thinker with a passion for technology. A collaborative team player who thrives in a dynamic environment. An effective communicator with strong interpersonal skills. A mentor and leader who inspires and guides junior engineers. A continuous learner who stays updated with industry trends and advancements.

【產品線描述】 Evolution Video Display 新興顯示器開發： 1. Gaming monitor controller for LCD, OLED and Mini-LED. 專業電競螢幕，極致沉浸競界曲面螢幕，遊戲體驗身歷其境 2. Public display controller for LCD and Micro/Mini-LED. 大型商用顯示器，極窄邊框拼接電視牆，電子白板 3. Electronic Vehicle Display Controller. AR/2D HUD(抬頭顯示器)，車用高速顯示介面 4. Advanced Projector Controller. 低延遲的遊戲投影機、短焦投影機、浮空影像顯示器 【工作說明】 1. Gaming 高階顯示器及戶外大型顯示看板 SoC 控制IC 設計, 驗證及量產測試 2. Video/Image/Color 相關演算法開發 3. 高階製程 whole chip 及 IP 整合, DFT 及 low power 設計流程及驗證 【必要條件】(符合下列一或多項者) 1. SoC IC 設計流程實務經驗 2. Whole chip 整合, STA timing 分析, 以及 APR co-work 經驗 3. CPU 架構與整合經驗 4. SoC internal bus 及 bridge 架構規劃及整合經驗 5. 高速數位介面 HDMI,DP, MHL,Vby1 等controller 電路開發經驗 6. 加解密(例如: HDCP 1.x, HDCP 2.2, ...) 硬體電路設計經驗 7. SDR/DDR Memory Controller 設計經驗 8. USB Type C controller 設計經驗 9. 對視訊影像處理,色彩轉換演算法開發有興趣或具經驗

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）開發相關的數位RD職缺。 【將負責的工作內容】 1. RTL design & verification 2. Customer support and debug 3. MIPI,USB, PCIE等高速介面IP開發。 4. 不同製程的IP Porting。 5. PHY Test Chip整合。 【條件與特質】 1. 具備數位設計流程經驗 (Synthesis/LEC/DFT/ATPG/STA) 2. 熟悉完整的Tape out flow 3. 熟悉MIPI,USB,DDR(LPDDR)相關高速混合信號介面(PHY)尤佳 4. 有數位IC設計工程師相關工作經歷3年以上 5. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

- Audio/Video framework debug - Linux/RTOS system debug

※Job Descriptions: 1.SoC design Job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, STA and FPGA verification. Hands-on capability is necessary ※Job Requirements: 1.Good at digital IC front-end design flow such as Verilog/VHDL RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA. 2.Experience in chip integration or subsystem design. 3.Familiar with shell scripts for design automation such as Perl language. 4.Familiar with ARM CPU and bus fabric is a plus. 5.Familiar with DDR, PCIe, MIPI or USB is a plus. 6.Fluent in English communication is a plus.

【產品線描述】 1. Timing controller for TV / Monitor / Notebook / Automobile panel display 2. Panel display quality improvement for high visual performance 3. Central control unit among panel, power IC and graphic card 【工作說明】 1. System integration, specification & feature create 2. Image quality algorithm development 3. DDR controller development, for high bandwidth efficiency 4. High speed & compatibility receiver development, co-work stability with TV SOC / Notebook graphic card 5. Transmitter & cell mapping development, highly compatible to all panel maker 6. Backend flow, including floorplan, synthesis and DFT 【必要條件】 1. Good at digital IC front-end design flow such as Verilog/VHDL RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA 2. Must have strong responsibility at personal job 3. Must have strong desire to extend knowledge base

1. Digital IP design and verification 2. SOC integration and verification

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 負責DDR Controller、DMA Controller模組開發與整合。 2. 設計SoC Bus Fabric，確保各模組間資料傳輸效能最佳化。 3. 參與數位IC設計流程，包括架構規劃、RTL設計、模擬與驗證。 4. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備3-5年數位IC設計經驗。 3. 熟悉DDR Controller、DMA Controller設計與整合。 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / SystemVerilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 具備多時脈域 (Clock Domain Crossing, CDC) 與低功耗設計經驗。 2. 熟悉ARM AMBA架構，如AXI、APB、AHB等匯流排標準。 3. 具備FPGA原型設計驗證經驗。 4. 熟悉腳本撰寫 (Perl、Python、TCL等)。 5. 具備SoC整合經驗或大規模數位電路設計開發經驗。 需具備技能： • DDR Controller / DMA Controller 設計整合 • SoC Bus Fabric 設計 • RTL 設計 (Verilog / SystemVerilog) • 匯流排協定 (AXI / AHB / APB) • 前端設計流程 (模擬、合成、時序分析) • 問題分析與解決能力 特別說明：此工作職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

【工作職責 (Responsibilities)】： ★ ARM series CPU integration ★ System bus architecture design and implementation 【Professional Experience】： ★ Experienced in ARM series CPU integration flow (ARM9, CA7, etc.) ★ Experienced in ARM cache, MMU, TCM design ★ Experienced in system bus architecture (AMBA AHB/AXI) design ★ Experienced in SoC chip integration 【符合條件 (Qualifications)】： 必須條件 (Minimum Qualifications)： ★ Outstanding problem analysis and debugging skills ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler 優秀條件 (Preferred Qualifications)： ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow ★ Nice to have experiences in C language.

Logic architecture design Algorithm design SoC design (MCU&Peripheral design) VHDL/Verilog logic design & simulation ASIC/FPGA synthesis flow

IP(including USB, PCIe, SATA, MIPI or SerDes) technical consultation for the customer, including IP usage, SoC integration and prototyping. -Digital IP support for the modeling and delivery, including simulation, synthesis, STA, formal equivalent check, FPGA emulation, and etc

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

【工作職責 (Responsibilities)】： ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. ★ Professional Experience ★ Experienced in image/video module design ★ Experienced in SoC front-end integration flow ★ In-house core algorithms' module design 【符合條件 (Qualifications)】： 必須條件 (Minimum Qualifications)： ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool ★ Familiar with video codec algorithm (H.264, H.265, H.266, AV1)

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

1.Ethernet IP設計及修改 2.RTL邏輯電路設計、驗證、合成 3.SoC IP設計、修改及整合 4.FPGA