「Digital IC Design / Verification Engineer」的相似工作

1.Integrated verification environment 2.Familiar with SoC level and IP level verification methodology 3.Develop verification plan and optimize verification flow 4.Familiar with verification methodology such as UVM, VMM, or OVM 5.Team player

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅About the job • 負責數位IC設計的功能驗證，確保設計符合規格要求。 • 建立UVM驗證平台，撰寫測試案例，進行模組與整合驗證。 • 熟悉AMBA (AXI/AHB/APB) 匯流排協定，應用於驗證環境。 • 使用C語言或SystemVerilog撰寫測試程式，進行功能覆蓋率分析與除錯。 • 與設計團隊，協同解決設計問題。 • 參與測試計畫制定、驗證策略設計及驗證報告撰寫。 ✅基本要求： • 電機、電子、資訊工程相關科系畢業，學士以上學歷。 • 具備3-5年數位IC設計驗證經驗。 • 熟悉AMBA (AXI/AHB/APB) 匯流排協定。 • 熟悉UVM驗證方法學，具備搭建UVM平台經驗。 • 熟悉SystemVerilog或C語言，能撰寫驗證測試程式。 • 熟悉模擬工具 (如VCS、NC-Verilog、ModelSim等)。 • 良好的問題分析與解決能力，具備團隊合作精神。 ✅加分條件： • 具備SoC驗證經驗。 • 熟悉FPGA驗證流程或原型驗證經驗。 • 熟悉低功耗驗證或性能分析經驗。 • 具備腳本開發能力 (Perl、Python、TCL等)。 ✅需具備技能： • AMBA (AXI/AHB/APB) Protocol • UVM驗證方法學(必要) • System Verilog / C 語言 • 功能驗證平台建置 • 模擬工具使用 (VCS / NC-Verilog / ModelSim 等) • 問題分析與除錯能力 • 驗證策略與覆蓋率分析

1. FPGA Design and Integration 2. Analog Digital Interface Design and Intergration 3. Digital BIST Design and Plan Chip CP/FT/MT Testing

We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. You will be responsible for the development and implementation of high speed interfaces, including TX/RX/Clocking/PLL. You will have hands on experience taking innovative integrated circuit designs at data rates of 50Gbps and higher from concept through silicon characterization. What you will be dong: - Define circuit requirements and complete design from schematic, layout, and verification to characterization. - Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. - Take responsibility for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. - Optimize circuit to meet the specifications for system performance. - Work with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. - Provide support for post-silicon bring-up and debugging. What we need to see: - Master of Science or foreign equivalent degree in Electrical Engineering, Computer Engineering or related field with strong analog design background. - Minimum 2 years analog design experience in industry - CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) - Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) - Experience in crafting test bench environments for component and top level circuit verification - Behavioral modeling of analog and digital circuits - Strong debugging and analytical skills - Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. - Strong communication skills and ability & desire to work as a great teammate are huge plus. - All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.

Do you expect to learn more the complete methodologies/solutions of design, implementation and analysis for a high-performance, power-efficient and area-effective chip developments? Do you also expect to explore the AI-driven solutions to accelerate chip design and improve efficiency throughout the design flow with AI-powered EDA tools? As part of our teams, you’ll have an opportunity to accordingly study, explore and design next-generation methodologies/solutions as follows. (1) Develop, maintain and optimize advanced methodologies for Frontend, Backend and Mixed-signal Design and implementation flows with the integrations of many corresponding EDA tools (Synopsys/Cadence/Siemens/Xilinx, ..., etc.) (2) Study, Explore and evaluate AI-driven design and implementation methodologies Currently, we expected this candidate is familiar with or interested in the related skill developments as follows. (1) Analog design flow and methodologies (Speed-up/Optimized simulation, mixed-signal co-simulation, EM/IR, Reliability Analysis, …, etc.). Knowledge of digital design flow using EDA tools (Synopsys, Cadence, Siemens (Mentor), …, etc.) is a plus (2) Programming/Scripting language like Perl, TCL, Python, C/C++, PERC, ..., etc. for flow automation (3) Be able to individually study and implement feasible solutions to resolve technical issues occurring in design and implementation flows. In our department, through kinds of flow developments and the related technical issue resolving, the following skill sets will finally be captured. (1) Extensive tool knowledge and experience for many different kinds of EDA tools and flow integration (Synopsys/Cadence/Siemens/Xilinx, …, etc.) used for Analog/Digital/FPGA Design and prototyping (2) Work with analog/digital design teams to coordinate a complicate project including Analog/Digital Designs for successfully tape out (3) Extensive AI-driven Analog/Digital/System Design and implementation flow We believe this position can be a great opportunity to extend your cross-fields IC design capabilities to include Analog, Digital and even System level designs for handling more complicate SoC design in the future.

1. Digital IP design and verification 2. SOC integration and verification

1. 熟讀規格書，建立VPLAN 2. 使用SystemVerilog 程式語言設計，UVM 建立模擬環境 3. 執行CRT驗證流程 (使用使用VERDI VCS NC等工具) 4. 跨部門合作溝通 (設計&軟體等部門)

請務必上官網投遞履歷:https://careers.synopsys.com/job/hsinchu/ddr-design-verification-engineer-sr-staff/44408/78985864320 Digital IP Verification, Staff Engineer Our group is working is working on cutting edge DDR controller design and verification targeting the current and next generation DDR technology, such as DDR5, LPDDR6. The position offers an excellent opportunity for a highly experienced verification engineer to work with a professional team of digital engineers responsible for delivering high-end designs from specification development to performing functional verification, performance analysis down to successful IP releases. The controller IP development is very dynamic and provides an endless list of challenges. This work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters. Does this sound like a good role for you? Responsibility and Key Qualification • This position is for leading edge IP verification. • Study standard specifications published by JEDEC. • Work on UVM methodology-based verification platform. • Study design micro architecture, implement high quality verification from defining verification spec, planning and implement infrastructure, down to analyze and debug regression failures, and reach full function coverage. • Work with design team to debug and fix RTL issues. • Work with VIP teams for VIP issues • Must be self-motivated, proactive, and able to achieve good quality while meeting tight deadlines. • Mentor junior engineers and work with multiple team members. • Good communication skills for interacting between different design groups and customer support teams are required. Preferred Experience • MSEE plus with a minimum of 5 years of experience in UVM-based verification methodology. And demonstrates good analysis and problem-solving skills. • Knowledgeable and experienced in UVM, assertions. Skills in Formal verification is a plus. • Knowledgeable in DDR is a plus. • Solid theoretical and practical background in AXI, CHI, CRYPTO and RAS is a solid plus. • Scripting experience in Shell, Perl, Python and TCL is a plus. • Be fluent in English, both speaking and writing. • Demonstrates good attitude in teamwork. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

TESDA 是一家快速成長的初創公司，正在尋找具有 5 年以上經驗的經理或處長和數名數位設計驗證工程師。 作為 TESDA 的設計驗證工程師，您將能夠接觸和驗證來自世界級公司的複雜SoC 設計，除了具有競爭力的薪資還有現金及股票分紅。 如果您正在尋找可以為個人職業和財務成長，提供巨大增長機會的職位以及工作與生活平衡，那麼 TESDA 就是您的理想之選！ 1. Responsible for system-level design verification 2. Develop test plans, test platforms, test cases, reference models, coverage models, and regression suites 3. RTL simulation/function verification/fault debugging 4. Drive and achieve coverage closure 5. Familiar with ARM or RISC-V & AMBA bus protocol is a plus. 6 Familiar with SVA/UVM test platform framework is a plus

1. Responsible for top-level or sub block pre-silicon design verification including test plan definition, test environment development in SV/UVM + C, test case creation, functional coverage coding and verification coverage analysis. 2. Work with validation team to support post-silicon debug.

Design verification: 1. SoC test environment build up 2. SoC test plan delivery 3. SoC test pattern build up 4. Regular regression and test report generation 5. IP verification support *備註：此職缺非研發替代役*

1.負責CPU設計的功能驗證，包括建立和維護驗證環境。 2.制定和實施約束隨機驗證策略，以確保CPU和相關外圍設計的功能正確性和性能。 3.運用覆蓋率驅動的方法來進行低功耗驗證，確保設計在各種功耗模式下的穩定性和效率。 4.實施形式化驗證和斷言基礎驗證，以提高設計的可靠性和降低錯誤率。 5.分析和處理驗證過程中出現的問題，與設計團隊緊密合作以進行問題定位和修正。 6.撰寫和維護相關的技術文檔，包括驗證計劃、測試案例和驗證報告。 7.跟踪最新的驗證技術和工具，不斷優化驗證流程和方法。

1. PMIC、LED driver IC驗證 2.驗證系統開發 3.客戶design in問題解決 4. FPGA驗證 5. IC規格訂定

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）開發相關的數位RD職缺。 【將負責的工作內容】 1. RTL design & verification 2. Customer support and debug 3. MIPI,USB, PCIE等高速介面IP開發。 4. 不同製程的IP Porting。 5. PHY Test Chip整合。 【條件與特質】 1. 具備數位設計流程經驗 (Synthesis/LEC/DFT/ATPG/STA) 2. 熟悉完整的Tape out flow 3. 熟悉MIPI,USB,DDR(LPDDR)相關高速混合信號介面(PHY)尤佳 4. 有數位IC設計工程師相關工作經歷3年以上 5. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

1.Ethernet IP設計及修改 2.RTL邏輯電路設計、驗證、合成 3.SoC IP設計、修改及整合 4.FPGA

通嘉致力打造工作/生活/健康兼具的職場環境，歡迎加入展開「通嘉就是你家」旅程! 本職務負責工作如下： 1. PD controller系統功能驗證 2.產品設計前之系統線路行為模擬分析、微控制器編成實測、WCA與實作驗證 3.編輯產品規格書與Design Tool 4.協助FAE進行產品推廣

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表： https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/Product---Test-Development-Engineer--Senior_3073181 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 QUALCOMM Technologies Inc. is the world leader in supplying integrated circuit solutions for cellular wireless standards and is the number one fabless semiconductor company. QTI is driving the next phase of wireless evolution and expanding quickly into adjacent IOT, Automotive, and Computing markets with advanced silicon/VLSI R&D. As a SerDes high speed ATE Test Engineer, you will have the opportunity to validate the most advanced high-speed SerDes IPs. Your responsibilities will range from developing ATE test solutions for production, design validation and characterization. You will be working on (but not limited to) Advantest 93000 tester platform, covering SerDes PHYs such as PCIe, UFS, USB2/3/4, DSI, CSI, and in-house proprietary high speed IP. You will work closely with the design, system, bench and vector teams to bring up ATE test cases, debug silicon issues. Additionally, you will collaborate with the hardware team to develop ATE test to meet production requirements. On top of NPI, supporting volume production (test time reduction, yield issue debug), will also be part of your role. Engineer will be driving failure analysis to completion with across stakeholders. The individual selected for the position, needs to be proactive, able to work in a fast-paced dynamic environment, enthusiastic to work as well as be passionate about delivering quality work. Minimum Qualifications · Bachelor's degree in Electrical Engineering, Computer Science, or related field. Preferred Qualifications · Master's Degree in Electrical Engineering. · Knowledge of Electrical/Electronic engineering fundamentals, digital, analog, mixed-signal and VLSI. · Knowledge of computer programming fundamentals (C/C++/Java/Perl) · Knowledge of signal integrity concepts Knowledge of SERDES IP working fundamentals (CTLE, CDR, etc.) Experience with the Advantest 93000 platform or other ATE platform · Knowledge of statistical concepts, analysis and techniques. · Knowledge in test automation development/scripting/debugging is a plus. · Strong verbal and written communications skills. · Independent, initiative and ability to overcome technical challenges. · Good organization and documentation skills.

Please apply this role from our career site with English resume attached: https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/Digital-SOC-Test-Engineer--Zhubei-_3063215 Thank you. ==================== 【Job Description】 Product and Test Development Engineering (PDTE) is looking for Digital Test Engineers who will create test solutions in support of New Product Introduction (Silicon Validation and Characterization) and Manufacturing Enablement of Qualcomm Silicon on Chip (SOC) products. The position offers growth/specialization opportunities within Digital Test Engineering (Processors, DDR, Sensors, DC, Test program integration, Structural ATPG Testing). The individuals selected for the positions will need to be able to work in a fast paced and dynamic environment and be passionate about delivering quality work. As a Product Test Engineer, you will create Automatic Test Equipment (ATE) code/test methods and participate in data reviews which will require close collaboration with Design, Design for Test (DFT), Process, Product, and Manufacturing Engineers. Minimum Qualifications Bachelor’s degree in engineering, Information Systems, Computer Science, or related field. Master of Electrical Engineering Preferred. 【Requirements】 Minimum 1 year of industry experience with hands on experience on Advantest 93K or Teradyne UFlex/IFlex. Understanding of VLSI technologies, familiarity with Digital Baseband products Proficiency in programming language C/C++/VB/Java/Python is a plus. Experience with data analytic tools such as O+, Data Power, Exensio and Machine Learning basics will be an added advantage. Familiarity with Digital Communication concepts. Knowledge of Semiconductor Physics. Ability to work with common test equipment (oscilloscope, spectrum analyzer, time interval analyzer, logic analyzer, network analyzer, etc). 【Educational Requirements】 • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

1. 熟悉 RTL design原理 2. 熟悉數位 IC 設計流程 3. 瞭解 MCU 動作原理 4. 使用 FPGA platform 開發