「設計驗證工程師」的相似工作

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅About the job • 負責數位IC設計的功能驗證，確保設計符合規格要求。 • 建立UVM驗證平台，撰寫測試案例，進行模組與整合驗證。 • 熟悉AMBA (AXI/AHB/APB) 匯流排協定，應用於驗證環境。 • 使用C語言或SystemVerilog撰寫測試程式，進行功能覆蓋率分析與除錯。 • 與設計團隊，協同解決設計問題。 • 參與測試計畫制定、驗證策略設計及驗證報告撰寫。 ✅基本要求： • 電機、電子、資訊工程相關科系畢業，學士以上學歷。 • 具備3-5年數位IC設計驗證經驗。 • 熟悉AMBA (AXI/AHB/APB) 匯流排協定。 • 熟悉UVM驗證方法學，具備搭建UVM平台經驗。 • 熟悉SystemVerilog或C語言，能撰寫驗證測試程式。 • 熟悉模擬工具 (如VCS、NC-Verilog、ModelSim等)。 • 良好的問題分析與解決能力，具備團隊合作精神。 ✅加分條件： • 具備SoC驗證經驗。 • 熟悉FPGA驗證流程或原型驗證經驗。 • 熟悉低功耗驗證或性能分析經驗。 • 具備腳本開發能力 (Perl、Python、TCL等)。 ✅需具備技能： • AMBA (AXI/AHB/APB) Protocol • UVM驗證方法學(必要) • System Verilog / C 語言 • 功能驗證平台建置 • 模擬工具使用 (VCS / NC-Verilog / ModelSim 等) • 問題分析與除錯能力 • 驗證策略與覆蓋率分析

Develop and maintain environment for SOC pre-silicon verification of: • RTL and netlist simulation • CRV for system fabric • Power-aware simulation • Formal CC and FPV • System level verification with SVA

請務必上官網投遞履歷:https://careers.synopsys.com/job/hsinchu/ddr-design-verification-engineer/44408/76799021424 Digital IP Verification, Staff Engineer Our group is working is working on cutting edge DDR controller design and verification targeting the current and next generation DDR technology, such as DDR5, LPDDR6. The position offers an excellent opportunity for a highly experienced verification engineer to work with a professional team of digital engineers responsible for delivering high-end designs from specification development to performing functional verification, performance analysis down to successful IP releases. The controller IP development is very dynamic and provides an endless list of challenges. This work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters. Does this sound like a good role for you? Responsibility and Key Qualification • This position is for leading edge IP verification. • Study standard specifications published by JEDEC. • Work on UVM methodology-based verification platform. • Study design micro architecture, implement high quality verification from defining verification spec, planning and implement infrastructure, down to analyze and debug regression failures, and reach full function coverage. • Work with design team to debug and fix RTL issues. • Work with VIP teams for VIP issues • Must be self-motivated, proactive, and able to achieve good quality while meeting tight deadlines. • Mentor junior engineers and work with multiple team members. • Good communication skills for interacting between different design groups and customer support teams are required. Preferred Experience • MSEE plus with a minimum of 5 years of experience in UVM-based verification methodology. And demonstrates good analysis and problem-solving skills. • Knowledgeable and experienced in UVM, assertions. Skills in Formal verification is a plus. • Knowledgeable in DDR is a plus. • Solid theoretical and practical background in AXI, CHI, CRYPTO and RAS is a solid plus. • Scripting experience in Shell, Perl, Python and TCL is a plus. • Be fluent in English, both speaking and writing. • Demonstrates good attitude in teamwork. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

1. Verify RISC-V SOC platform including MMU, interrupt controller, security, bus bridge, bus fabric, and peripheral IPs. 2. Build testbench, develop and maintain in-house VIP. 3. Create rand constraint conditions, analysis coverage holes and fill them. 4. Create function coverage points to make sure all functions are under test.

TESDA 是一家快速成長的初創公司，正在尋找具有 5 年以上經驗的經理或處長和數名數位設計驗證工程師。 作為 TESDA 的設計驗證工程師，您將能夠接觸和驗證來自世界級公司的複雜SoC 設計，除了具有競爭力的薪資還有現金及股票分紅。 如果您正在尋找可以為個人職業和財務成長，提供巨大增長機會的職位以及工作與生活平衡，那麼 TESDA 就是您的理想之選！ 1. Responsible for system-level design verification 2. Develop test plans, test platforms, test cases, reference models, coverage models, and regression suites 3. RTL simulation/function verification/fault debugging 4. Drive and achieve coverage closure 5. Familiar with ARM or RISC-V & AMBA bus protocol is a plus. 6 Familiar with SVA/UVM test platform framework is a plus

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

ASIC design virification engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. As a senior member in the team, he/she will focus on improving the design verification methodology and flow. Work cross-function with analog and DSP teams to achieve high-quality analog mixed-signal verification. The responsibilities include but not limited to: *Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications. *Use and improve UVM DV environment *Improve the design methodology and flow. *Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive *SerDes IP solutions for all the Marvell product lines. *Provide the support to the product teams, for both pre and post silicon

對以下項目有相關經驗，或有興趣者，歡迎來信洽談 • 類比及數位電路特性驗證經驗 • 使用FPGA 驗証，熟悉soc開發平台 • 制定驗證計畫、設計驗證方法、分析數據資料 • 開發自動化驗證輔助工具 • 產品應用規劃，PCB電路設計及layout • 晶片可靠度分析、量產良率分析

※ Job Contents: 1. DDR/HBM controller IP design 2. DDR/HBM IP customer support 3. Execute digital IP front-end flow ※ Requirements: 1. 3-years digital IC design experiences 2. Senior/Technical Manager: 8-years digital IC design experiences 3. Familiar with DDR protocol is a plus 4. Familiar with AMBA interface is a plus 5. Familiar with IC front-end design flow such as Lint/CDC, Synthesis, LEC/formality, PrimeTime STA is a plus

SERDES IP of TCON / Driver IC驗證、分析與問題解析。

1. 熟讀規格書，建立VPLAN 2. 使用SystemVerilog 程式語言設計，UVM 建立模擬環境 3. 執行CRT驗證流程 (使用使用VERDI VCS NC等工具) 4. 跨部門合作溝通 (設計&軟體等部門)

1. Use Verilog/SystemVerilog languages to verify design at block level or full chip level 2. Verification plan creation and implementation(test environment setup, modeling, test-case development and execution), coverage analysis, and regression cleanup 3. Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment. *備註：此職缺非研發替代役*

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表： 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446697376843 【Job Description】 As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. 【Job Summary】 This position involves designing and implementing Low-power, High Performance, area-efficient embedded memory (CPUL1/L2, SRAM, register files, etc.) circuits and architectures. Position will be located in APAC-TW metropolitan region. 【Responsibilities】 Develop memory architectures and circuit implementation techniques. Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation. 【Qualifications in the following areas are preferred】 - 3+ years of academic or professional experience designing embedded memories for SoC applications - Strong Technical expertise in CPUL1/L2, Compiler SRAM/Register File architectures and advanced custom circuit implementations. - Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation - Physical implementation (layout) and layout supervision - Advanced technology nodes 【Qualifications in the following areas are a plus】 - Experience with tight pitch-matched memory layout designs - Understanding of physical implementation impact on circuit performance - Familiarity with variation-aware design in nano-meter technology nodes - Experience with low power design features and flows

Position Description: • Work closely with Sales team to identify and scope opportunities for Cadence Emulation and Prototyping products. • Plan, execute and manage key technical evaluations and benchmark with existing and potential customers. • Train, ramp-up and accompany customer project. • Conduct basic and advanced trainings, presentations and demos as necessary. • Providing technical expertise to address clients’ queries, which need expert involvement. • Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement. Position Requirements: • Minimum 3 years hands-on expertise on SoC design & verification technique • Design experience in Verilog/VHDL for IP or SoC chip level is required • Knowledge of System Verilog/VHDL and HDL simulators is required • Experience with hardware emulator or FPGA prototyping is a big advantage • Knowledge of Unix and Linux is highly desired • Familiar with shell/python/tcl etc. script language is a plus • Advanced Verification Methodology like UVM is a plus • Strong verbal and written communication skills in English • Strong teamwork skills with good human relationship • Ability to travel within Asia Pacific region for onsite customer visits is a plus.

通嘉致力打造工作/生活/健康兼具的職場環境，歡迎加入展開「通嘉就是你家」旅程! 本職務負責工作如下： 1. PD controller系統功能驗證 2.產品設計前之系統線路行為模擬分析、微控制器編成實測、WCA與實作驗證 3.編輯產品規格書與Design Tool 4.協助FAE進行產品推廣

1. 相關面板系統驅動應用 2. TV/MNT/NB TCON IC 相關驗證 3. 驗證平台設計與驗證 熟悉eDP PSR I/II ,DSC and other special feature verification & trouble-shooting尤佳

1. RTL design & simulation 2. Cell base design flow 3. Digital verification 4. Design documentation 孰悉以下工具: Verilog coding, 與 Cell base design flow 具有以下相關經驗尤佳: 1. Memory controller 相關經驗 2. low power design flow 相關經驗 3. MCU開發相關經驗 4.FPGA 開發與 SOC整合和驗證

Please apply this role from our career site with English resume attached: https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/Digital-SOC-Test-Engineer--Zhubei-_3063215 Thank you. ==================== 【Job Description】 Product and Test Development Engineering (PDTE) is looking for Digital Test Engineers who will create test solutions in support of New Product Introduction (Silicon Validation and Characterization) and Manufacturing Enablement of Qualcomm Silicon on Chip (SOC) products. The position offers growth/specialization opportunities within Digital Test Engineering (Processors, DDR, Sensors, DC, Test program integration, Structural ATPG Testing). The individuals selected for the positions will need to be able to work in a fast paced and dynamic environment and be passionate about delivering quality work. As a Product Test Engineer, you will create Automatic Test Equipment (ATE) code/test methods and participate in data reviews which will require close collaboration with Design, Design for Test (DFT), Process, Product, and Manufacturing Engineers. Minimum Qualifications Bachelor’s degree in engineering, Information Systems, Computer Science, or related field. Master of Electrical Engineering Preferred. 【Requirements】 Minimum 1 year of industry experience with hands on experience on Advantest 93K or Teradyne UFlex/IFlex. Understanding of VLSI technologies, familiarity with Digital Baseband products Proficiency in programming language C/C++/VB/Java/Python is a plus. Experience with data analytic tools such as O+, Data Power, Exensio and Machine Learning basics will be an added advantage. Familiarity with Digital Communication concepts. Knowledge of Semiconductor Physics. Ability to work with common test equipment (oscilloscope, spectrum analyzer, time interval analyzer, logic analyzer, network analyzer, etc). 【Educational Requirements】 • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

1. EDA tool management including EDA tools evaluation and purchase support. 2. SoC IC design flow creation, automation, management, and enhancement. 3. Design/Layout platform, library/IP importing, QA & management. 4. IC layout verification programs creation and maintenance ability. 5. Script programs creation and maintenance for improvement and robust of design flow. 6. Support of design & layout problem solving on EDA tools or design flow. 7. Support of EDA tools related IT management.

【產品線說明】 TDDI顯示觸控整合產品。TDDI整合Display/Touch的IC，除了觸控相關技術外，還做為兩者的整合橋樑，發揮1加1大於2的價值！ 【工作內容】 1. 驗證新IC觸控相關功能之可靠性與正確性。 2. 開發/研究產品可靠性之測試項目。 3. 開發/維護產品測試之Firmware流程。 4. 產品故障分析、測試環境故障分析。 5. 跟客戶和廠內跨部門溝通產品驗證相關工具、流程、方法等需求。 【必要條件】 1. 電機/資訊/電控相關背景碩士畢業。 2. 熟C程式語言。 3. 有基礎電子電路和儀錶設備控制經驗。 4. 細心、善於人際互動與溝通、抗壓性高。