「邏輯設計工程師」的相似工作

1. 影像品質調校：負責影像品質參數調整及確認，包括3A、HDR、Color Adjustment、DeNoise、Sharpness等，確保影像表現達到最佳狀態。 2. 影像測試與驗證：熟悉IQ測試工具，執行影像品質測試與分析，並產出相關驗證報告。 3. 建立測試計畫與問題分析：根據產品需求建立測試環境，設計測試項目，執行測試、記錄結果，撰寫測試報告，並能清楚描述問題點與改善建議。 4. 具備兩年以上主觀與客觀IQ調適經驗. 您將有機會學習並拓展其他產品類別的驗證測試專長，為自身職涯發展加分 1. 相容性與可靠度：與IC影像品質驗證的同時，學習PC IO相容性與可靠度測試，提升跨領域測試能力。 2. 認證：相關如WHQL、USBIF、PCI-SIG、Thunderbolt、VESA.

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager VICI Holdings 威旭資訊是一間專注於高頻、造市及套利交易的公司，我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊，並具備華爾街等級的FPGA設計技術，據此打造低延遲全自動交易系統；同時，交易策略橫跨股票、期貨及衍生性商品，且每日全球交易市值達數百億台幣。 我們以人為本，提供開放且自由的工作環境，讓夥伴可以專注於研究與創新，同時，透明且扁平化的組織架構，讓所有人都可以在組織裡發聲並發揮潛能。 我們的研發團隊是技術導向、喜歡研究與實驗、樂於求新求變及接受挑戰以追求極致完美的研發團隊，將來工作中您會高強度的使用軟硬體開發相關的專業知識，如您有高度熱忱學習，渴望快速成長，歡迎加入！ 【工作職責】 ・超高速I/O介面設計(PCIE/ Ethernet/ DDR etc.) ・數位模擬 ・傳輸協定層開發 ・AI硬體實現 ・硬體延遲最佳化 【專業能力需求】 ・熟悉 Verilog之語言特性，具備硬體描述語言與數位設計能力。 ・具備學習新知與研讀規格的能力與毅力。 ・具備應對複雜設計和實施有效解決方案的能力。 【面試流程】可能視情況調整流程順序 履歷篩選 -> Coding Test -> 線上AI面試 -> 現場考題 ＆現場面試 -> HR面試

1.Ethernet IP設計及修改 2.RTL邏輯電路設計、驗證、合成 3.SoC IP設計、修改及整合 4.FPGA

1.依據Spec要求做設計,負責模組層級電路設計 2.遠端連線,在家工作

1. 熟讀規格書，建立VPLAN 2. 使用SystemVerilog 程式語言設計，UVM 建立模擬環境 3. 執行CRT驗證流程 (使用使用VERDI VCS NC等工具) 4. 跨部門合作溝通 (設計&軟體等部門)

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

1. RTL design and simulation 2. ASIC/SOC prototyping and Validation 3. FPGA synthesis and implem *備註：此職缺非研發替代役*

1. RTL design & simulation 2. Cell base design flow 3. Digital verification 4. Design documentation 孰悉以下工具: Verilog coding, 與 Cell base design flow 具有以下相關經驗尤佳: 1. Memory controller 相關經驗 2. low power design flow 相關經驗 3. MCU開發相關經驗 4.FPGA 開發與 SOC整合和驗證

針對數位動作設計並撰寫 RTL coding,模擬 pattern, 跑 simulation, synthesize.

ASIC design virification engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. As a senior member in the team, he/she will focus on improving the design verification methodology and flow. Work cross-function with analog and DSP teams to achieve high-quality analog mixed-signal verification. The responsibilities include but not limited to: *Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications. *Use and improve UVM DV environment *Improve the design methodology and flow. *Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive *SerDes IP solutions for all the Marvell product lines. *Provide the support to the product teams, for both pre and post silicon

Molex possesses a rich heritage in the optical industry. We provide the highest performing and field-proven wavelength management solutions from components, modules to integrated line-cards. Continuous innovation in passive component function integration, miniaturization, and manufacturing automation, cutting edge WSS and amplification technology and comprehensive optical, mechanical, electrical and software design capabilities enable us to serve the needs of high-density, high-bandwidth, and flexible optical networks of telecom, datacom, hyperscale datacenter and supercomputing. In New Taipei, Taiwan, we serve global clients in telecom and datacom industries in providing innovative optical modules and subsystems to support our customer’s next generation networks. We are looking for a Sr. FPGA Engineer. This person will be responsible for architecting, designing, developing, simulating, optimizing, testing, and debugging innovative FPGA solutions and code with a focus on optical networking products and embedded control. You will be responsible for leading FPGA logic, firmware, and software from concept to production, collaborating with other engineers, scientists, and customers, and ensuring the highest quality and performance of our products. What You Will Do • Architect, design, develop, simulate, synthesize, close timing, test, debug, and optimize FPGA logic firmware and software using Verilog and other tools • Implement various control and digital signal processing algorithms and systems on FPGA platforms • Optimize FPGA designs for performance, power, resource utilization, etc. • Troubleshoot and debug FPGA issues and provide technical support • Create and maintain test plans, technical documents, reports, and presentations, generate engineering changes, release designs, evaluate vendors, analyze issues and determine root cause • Participate in design reviews and provide feedback on the design of FPGA systems and implementations • Work with other team members to optimize and finalize design for full production and to meet all specifications • Research and evaluate new FPGA technologies, trends and vendors, select devices • Provide technical support to customers and suppliers • Perform other related duties as assigned by management • Mentor other team members Who You Are (Basic Qualifications) • Bachelor’s or Master’s degree in Electrical Engineering, or related technical field or discipline • At least 5 years of experience in FPGA design, debug, and development • Proficient in Verilog, SystemVerilog, or other HDL languages • Proficient with Xilinx, Altera, or other FPGA products and development environments • Experience with communication protocols, such as PCIe, I2C, SPI, SGMII, ethernet, other industry standard interfaces, digital signal processing, embedded systems, and control algorithms • Knowledge of FPGA design methodologies, best practices, and tools • Demonstrated ability to analyze information and solve problems • Ability to understand schematics and other PCBA board related items • Ability to speak and communicate in English What will put you ahead • MS or PhD degree in Electrical Engineering, or related field related technical discipline • 8+ years of FPGA system design and simulation • Experience developing with Xilinx SoC parts, such as Zync UltraScale+ and Zync 7000, and tools such as ISE, ModelSim, Vivado • Experience with scripting languages, such as Python or TCL

Do you expect to learn more the complete methodologies/solutions of design, implementation and analysis for a high-performance, power-efficient and area-effective chip developments? Do you also expect to explore the AI-driven solutions to accelerate chip design and improve efficiency throughout the design flow with AI-powered EDA tools? As part of our teams, you’ll have an opportunity to accordingly study, explore and design next-generation methodologies/solutions as follows. (1) Develop, maintain and optimize advanced methodologies for Frontend, Backend and Mixed-signal Design and implementation flows with the integrations of many corresponding EDA tools (Synopsys/Cadence/Siemens/Xilinx, ..., etc.) (2) Study, Explore and evaluate AI-driven design and implementation methodologies Currently, we expected this candidate is familiar with or interested in the related skill developments as follows. (1) Analog design flow and methodologies (Speed-up/Optimized simulation, mixed-signal co-simulation, EM/IR, Reliability Analysis, …, etc.). Knowledge of digital design flow using EDA tools (Synopsys, Cadence, Siemens (Mentor), …, etc.) is a plus (2) Programming/Scripting language like Perl, TCL, Python, C/C++, PERC, ..., etc. for flow automation (3) Be able to individually study and implement feasible solutions to resolve technical issues occurring in design and implementation flows. In our department, through kinds of flow developments and the related technical issue resolving, the following skill sets will finally be captured. (1) Extensive tool knowledge and experience for many different kinds of EDA tools and flow integration (Synopsys/Cadence/Siemens/Xilinx, …, etc.) used for Analog/Digital/FPGA Design and prototyping (2) Work with analog/digital design teams to coordinate a complicate project including Analog/Digital Designs for successfully tape out (3) Extensive AI-driven Analog/Digital/System Design and implementation flow We believe this position can be a great opportunity to extend your cross-fields IC design capabilities to include Analog, Digital and even System level designs for handling more complicate SoC design in the future.

1. Use Verilog/SystemVerilog languages to verify design at block level or full chip level 2. Verification plan creation and implementation(test environment setup, modeling, test-case development and execution), coverage analysis, and regression cleanup 3. Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment. *備註：此職缺非研發替代役*

1. Ethernet SerDes高速介面數位設計 (USXGMII, 25G Base-R) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL), 和軟體同仁合作進行相關驗證 3. 具有高速介面或 high level synthesis實作經驗或FPGA實作經驗者尤佳

1. RTL coding, simulation and verification 2. 高速介面IP開發或演算法硬體電路設計 3. PHY test chip整合

1. Maintain and support front end design flow framework such as lint, synthesis, formality, and timing closure 2. Coordinate with IP owners for front end implementation 3. Coordinate with front end engineers and back end engineers for report analysis 4. Perform critical module implementation if needed 5. Utility development *備註：此職缺非研發替代役*

瞭解mixed-mode ic或MCU系統，針對數位動作撰寫 RTL coding, 設計 pattern, 跑 simulation, synthesize, FPGA驗證

1. DDR PHY/ controller開發驗證相關工作 2. RTL coding/synthesis/simulation/verification

• 工作職責 FPGA 設計、模擬與功能驗證 • 必要條件 具 FPGA 數位電路設計能力 熟悉運用FPGA開發工具，對數位電路設計進行偵錯、驗證 • 加分條件 熟悉乙太網路、 DDR介面以及基本的IO通信介面 熟悉Xilinx開發環境，具備實作經驗者尤佳 熟悉數位微波系統基頻設計 熟悉ARM架構

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者