Synopsys Taiwan Co., Ltd._台灣新思科技股份有限公司

請務必上官網投遞履歷:https://careers.synopsys.com/job/hsinchu/ddr-design-verification-engineer/44408/76799021424 Digital IP Verification, Staff Engineer Our group is working is working on cutting edge DDR controller design and verification targeting the current and next generation DDR technology, such as DDR5, LPDDR6. The position offers an excellent opportunity for a highly experienced verification engineer to work with a professional team of digital engineers responsible for delivering high-end designs from specification development to performing functional verification, performance analysis down to successful IP releases. The controller IP development is very dynamic and provides an endless list of challenges. This work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters. Does this sound like a good role for you? Responsibility and Key Qualification • This position is for leading edge IP verification. • Study standard specifications published by JEDEC. • Work on UVM methodology-based verification platform. • Study design micro architecture, implement high quality verification from defining verification spec, planning and implement infrastructure, down to analyze and debug regression failures, and reach full function coverage. • Work with design team to debug and fix RTL issues. • Work with VIP teams for VIP issues • Must be self-motivated, proactive, and able to achieve good quality while meeting tight deadlines. • Mentor junior engineers and work with multiple team members. • Good communication skills for interacting between different design groups and customer support teams are required. Preferred Experience • MSEE plus with a minimum of 5 years of experience in UVM-based verification methodology. And demonstrates good analysis and problem-solving skills. • Knowledgeable and experienced in UVM, assertions. Skills in Formal verification is a plus. • Knowledgeable in DDR is a plus. • Solid theoretical and practical background in AXI, CHI, CRYPTO and RAS is a solid plus. • Scripting experience in Shell, Perl, Python and TCL is a plus. • Be fluent in English, both speaking and writing. • Demonstrates good attitude in teamwork. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

The primary focus of this Verification Applications Engineer is to support the sale and adoption of the Synopsys Verification solution. As a Verification AE, you will be driving the effort to enable the verification methodology and solution for customers using Synopsys Verification tools. Must possess in-depth knowledge of RTL low power design, verification and power analysis. You will work directly with customers to assist with the deployment of the verification tools and methodologies, resolve technical issues and provide technical training.. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules. Education Requirements: o College degree(or above) in Electrical Engineering/ Computer Science. Skills/Experience: o Good team player and communication skills. o Good Knowledge of RTL coding , Chip Design experience or verification env. architect experience,. Understanding ＂big picture＂ at the ASIC architectural and system level with experience on real block/soc verification experience . o Testbench creation and Verification regression o Familiar with scripting language like Perl/Python/Tcl/CSH/BASH/Makefile. o Fluent English on reading/writing (esp technical spec ). Nice to have: o Experience on UVM verification or implementation o Experience on UPF verification or implementation o Experience on power reduction and analysis on RTL design. o Familiar with one of following protocols : AMBA/USB/PCIE/DDRx . o Familiar with one of following tool : VCS/Verdi/Spyglass

Synopsys is uniquely positioned to offer the most complete verification solution in market today.The emulation platform of Synopsys verification flow, it’s the industry’s performance & capacity leader in Emulation. As an Application Engineer for emulation, candidate will be primarily responsible for successful deployment and evaluation of Synopsys emulation solution. He/She will closely work with customers, Sales, Marketing and R&D teams to resolve complex technical issues, presales evaluations, post-sales support, develop collaterals. Candidate will help analyze and resolve complex design verification and software validation issues for customers cutting edge ASIC/SoC designs. The position offers a great opportunity to grow by learning state-of-art verification flows from Synopsys. Requirements: 1.College degree(or above) in Electrical Engineering/ Computer Science. Skills/Experience 2.Good team player and communication skills. 3.Good Knowledge of RTL coding , Chip Design experience or verification env. architect experience,. Understanding ＂big picture＂ at the ASIC architectural and system level with experience on real block/soc verification experience . 4.Good expertise on emulators like Palladium/Veloce/Zebu or FPGA compile/runtime/debug are preferred. 5.Familiar with scripting language like Perl/Python/Tcl/CSH/BASH/Makefile. 6.Fluent English on reading/writing (esp technical spec ). 7.Familiar with one of following protocols : AMBA/USB/PCIE/Ethernet Nice to have: 1.Experience on driver/FW FPGA development. 2.Familiar with one of following tool : VCS/Verdi/ProtoCompiler

Responsible for designing, developing, troubleshooting, or debugging software programs. Develops software tools including operating systems, compilers, routers, networks, utilities, databases and internet-related tools, etc. Determines hardware compatibility and/or influences hardware design. Usually developing professional expertise, and may apply company policies and procedures to resolve a variety of issues. At a minimum, has working knowledge of work area and general proficiency with tools, systems, and procedures required to accomplish the job. Exercises judgment to determine appropriate action. Implementations and solutions are reviewed for accuracy and overall adequacy. Builds productive internal/external working relationships.

Responsible for designing, developing, troubleshooting, or debugging software programs. Develops software tools including data structures, algorithms, compilers, utilities, and databases etc. tools, etc. Experience in programming software for algorithms, unix operating system, and/or job control languages, and some knowledge of software capabilities. Designs algorithms and data structures. Experience on development of complex software projects, familiarity with C/C++ coding, and a strong background in data structures and algorithms. Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills. Prior knowledge and experience of CAD tool development are required. Possesses a solid understanding of specialization area plus working knowledge of one other related area. Resolves issues in creative ways. Exercises independent judgment in selecting methods and techniques to obtain solutions. Executes projects from start to completion. Contributes to moderately complex aspects of a project. Determines and develops recommendations to solutions. Works on team-driven or task-oriented projects. Networks with senior internal and external personnel in own area of expertise.

Job Description · Become a trusted advisor to the customer for EDA tools · Coordinate with sales and marketing to find new opportunities, position ICV for success, and increase ICV business · Influence the buying decisions through technical success (product demos, tapeouts, evaluations, etc) · Enable customers to use product successfully and autonomously (installation, script assistance, training, etc) · Deploy and train customers on new and advanced product features · Solve customer problems to build trust with product · Manage issues (bugs) to resolution with customer and product team · Drive product enhancements as needed to support business · Develop workarounds to meet customer deliverables · Educate product team and peers about technical trends and opportunities Key Qualification · Master Degree in Electrical Engineering,/ Computer Science · Experience in digital design/ physical design or physical verification of semiconductors is a plus · UNIX navigation and scripting (Perl, Tcl and Python) · Presentation skills

We are searching for a technical architect with positive thinking and collaborative attitude. Your role is to provide strategic guidance to meet customer needs and expectations cost-effectively. Responsibilities and Duties ● Drive technical innovation and automation for custom design solutions ● Review and examine product feedback from customers and application partners ● Collaborate with field and sales teams on customer engagement ● Define technical roadmap and specifications while balancing with business goals, resources, and schedule Qualifications and Skills ● A master's degree in EE or CS is required ● 15 years' experience in large-scale software development and programming (C/C++, TCL/Python, Qt) ● Physical layout experience is a plus ● Proficient written and verbal communication skills in English ● Drive results ● Create networks with crucial action makers

Role and Responsibility - To be the product professional to drive the success of Synopsys RTL2GDS design flow and tools focusing on Design Compiler, Fusion Compiler and RTL Architect. - Be the interface between customers and product teams to deploy the synthesis solutions to help customers successful with their design requirements - Be responsible for product application, product deployment, professional training and benchmark. Works closely with R&D and sales team - Able to work exclusively as well as in a team environment - Experienced user of synthesis tools such as Design Compiler, Fusion Compiler, RTL Architect or other EDA tools. Advanced nodes, physical design, low power, DFT and formal check experience is a plus - Good scripting skills and understanding of RTL - Good understanding of RTL2GDS design flow, high performance design, low power design methodologies - Self-motivated & solid communication skill - Good command of English and people skills are required Preferred Experience - BS/MS with 5+ years of direct hands-on design experience in using frontend synthesis and/or backend physical design Place & Route tool

● Responsible for designing, developing, troubleshooting, or debugging software programs. ● Develops software tools including operating systems, compilers, routers, networks, utilities, databases and internet-related tools, etc. ● Determines hardware compatibility and/or influences hardware design.

請務必投遞官網(50259BR): https://sjobs.brassring.com/TGnewUI/Search/home/HomeWithPreLoad?PageType=JobDetails&partnerid=25235&siteid=5359&jobid=2008002#jobDetails=2008002_5359 At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules. Applications Engineer We're looking for an Applications Engineer to join our team. Does this sound like a good role for you? This is an exciting opportunity to be part of a fast-paced Applications Engineering team that is changing the industry landscape in the area of library characterization and transistor-level timing analysis. As a specialist in characterization, you will work closely with customers to solve complex technical challenges in areas of statistical analysis, electro-migration, timing & power modeling, and signal integrity analysis. Through innovative techniques and ideas, you will help enable customers to accurately validate these components in standard cells, high-speed custom macros, low-power circuits, complex programmable logic circuits, and memory designs. Key Qualifications BSEE/MSEE 3+years of experience in at least one area - custom digital design, standard cell design/characterization, memory design/characterization 1.Solid understanding of timing, power, statistical and electro-migration characterization, and signal integrity 2.Experience with applications deployment on cloud architectures (AWS, Azure, etc) desired 3.Knowledge of static timing analysis and path level correlation using STA tools desired 4. Experience with industry-standard tools like Siliconsmart, NanoTime, Liberate, NCX, PrimeTime, PrimePower, and Library Compiler 5.Working knowledge of Spice tools like Finesim, CustomSim, Hspice, Eldo, and Spectre 6.Working knowledge of scripting languages like Unix Shell, Perl, TCL 7.Self-motivated, excellent time management, and able to work autonomously on resolving technical problems 8.Strong interpersonal and communication skills (prior AE experience is a plus) Preferred Experience 9.Pre-sales activity: Participates in technical benchmarks, methodology presentations, and demos to articulate the advantage of our solution 10.Post-sales support: Participates in customer tape-outs using Synopsys' products, as well as customer training and on-site support 11.Drives product improvements and innovation by bringing customer inputs and vision into Synopsys R&D 12.Provide skillset growth in customer relationship management Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

The Job is for a first level management role in Custom Router R&D team of Synopsys Custom Compiler. In addition to manage and mentor 2-3 junior engineers, the candidate has to take technical responsibilities including feature development, code review, designing software architecture. To work with the broader team, he is expected to have good communication, coordination, and partnership skills. The expertise in EDA area is necessary and better to have physical design automation relating experience. * Qualifications: 1. MS/Ph.D. degree in Electrical Engineering, Computer Science 2. 5+ years of physical design related experience in EDA industry 3. Strong programming skills in C++/TCL/Python, proficient in data structure, 4. algorithm, large scale software development 5. Obsessed with creating clean code, but not hesitant about legacy code 6. Bright, willing to share and teach * Extra plus: Experience in developing EDA automation methodology and tools Familiar with advanced design rule and how the checking works Strong organizational skills for engineering projects Good communication and presentation skills

請務必在官網完成投遞履歷: https://jobs.brassring.com/TGnewUI/Search/home/HomeWithPreLoad?PageType=JobDetails&partnerid=25235&siteid=5359&Areq=50626BR We are looking for motivated Applications Engineer to help our customers succeed in using state of the art Synopsys static timing characterization and library modelling tool PrimeTime. The primary focus of the Applications Engineer is to help our customers with the adoption and continuous usage of static timing analysis, enabling Chip Design Customers achieve best Power/Performance/Area Goals. Synopsys’ PrimeTime & Signoff tool is an advanced transistor-level static timing characterization and library modelling solution that addresses the existing and emerging challenges in custom and memories design. It offers predictability and improved productivity to designers. Its concurrent timing and SI features as well as advanced variation aware timing enable designers to accurately and quickly identify design issues early-on and avoid expensive late-finding of problems in silicon. The engineer will closely work with PrimeTime & Signoff R&D team, to influence technologies/solution roadmaps and provide R&D team with accurate input from field, helping them focus on the most critical design challenges. The engineer will work with other Synopsys AEs, ensuring overall consistency of end-to-end design flow and meet customer needs. Main responsibilities: · Engineer will use in-depth product knowledge to provide technical expertise to customer to help solve day to day technical problems and help develop word class static timing methodologies. · Provide consultation to prospective users and/or product capability assessment and validation. · Provide tool trainings. · Provides technical expertise to sales staff through sales presentations and product demonstrations. · Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. Requirements: We are looking for an innovative, motivated and dependable person, with at least BSc degree and five years of recent hands-on experience including: · Solid knowledge of static timing concepts and engineering fundamentals. · Exceptional expertise in transistor-level design to debug circuit level issues. · Good knowledge of TCL and other scripting languages. · Very good communication and social skills. Plus: · Transistor based STA experience. · PrimeTime & Signoff experience highly desirable. · Memory design, characterization experience highly desirable. · Experience in advanced technology nodes preferred.

請務必上官網投遞履歷:https://careers.synopsys.com/job/hsinchu/ddr-design-engineer/44408/76798998704 Digital IP Design, Staff Engineer Our group is working on cutting edge DDR controller design and verification targeting the current and next generation DDR technology, such as DDR5, LPDDR5, LPDDR6 and HBM4. The position offers an excellent opportunity to work with a professional team of digital design engineers responsible for delivering high-end designs from specification development to performing functional design, performance tests down to successful IP releases. The controller IP development is very dynamic and provides an endless list of challenges. This work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters. Does this sound like a good role for you? Responsibility and Key Qualification • Study standard specifications published by JEDEC, define micro architecture at block level based on IP architecture. • Work on RTL design based on predefined coding style, SVA is also included, clean RTL check violations in lint, CDC, DFT and synthesis. • Work with verification team to debug and fix RTL issues. • Good knowledge of back-end synthesis tools DC/PT is required. • Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines. • May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise. • Good communication skills for interacting between different design groups and customer support teams are required. Preferred Experience • MSEE plus a minimum of 5 years of digital design experience in the industry. • Has strong desire to learn and explore new technologies. • Demonstrates good analysis and problem-solving skills. • Knowledge in interface technologies such as DDR, HBM, PCIe is a plus. • Solid theoretical and practical background in AXI, CHI, CRYPTO and RAS is a solid plus. • Good experience is co-working with UVM-based verification is a plus. • Scripting experience in Shell, Perl, Python and TCL is a plus. • Interacting with Application Engineers for customer support. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

請務必上官網投遞履歷: https://careers.synopsys.com/job/hsinchu/hardware-engineering-sr-staff-engineer/44408/70025497744 Job Description and Requirements: Synopsys is uniquely positioned to offer the most comprehensive prototyping solution in market today. HAPS system is the prototyping solution of Synopsys ASIC validation flow, it’s the industry’s performance & capacity leader in prototyping. As a hardware designer, candidate will be primarily responsible for successful deployment of HAPS related board design including its validation. He or she will closely work with AE and customers to propose and design/validate protocol interface card solution on HAPS which can be a reference design kit. Candidate will also help customer review HAPS daughter board schematics and layout. The position offers a great opportunity not only to grow by learning kinds of peripheral interface solution but also communication skills and project management capability from Synopsys. Education Requirements: -College degree(or above) in Electrical Engineering/ Computer Science Skills/Experience -Good team player and communication skills -Good experience on porting RTL to FPGA using Vivado or Synplify/Protocompiler/Protosynthesis or 3rd party FPGA synthesizer -Good expertise on 3rd parity FPGA prototyping platform like HAPS/S2C/TalentPros etc. with related FPGA compile/runtime/debug experience are preferred -Experience on hardware board design tools such as Orcad/PADS and Allegro -Familiar with one of following protocols : MIPI/HDMI/AMBA/USB/PCIE/DDRx -Familiar with simulation and debug tools such as VCS and Verdi -Familiar with scripting language like Perl/Python/Tcl/CSH/BASH/Makefile -Fluent English on reading/writing (esp. technical spec) Nice to have: -Experience on multi FPGA partition with well timing constraint knowledge -Experience on Xilinx high speed IO application such as using GTH/GTY -Experience on Xilinx EDK development -Experience on Driver/FW/SOC FPGA debug/development

請上官網投遞此職缺: https://careers.synopsys.com/job/hsinchu/ddr-hbm-digital-design-and-verification-manager/44408/76947040624 You Are: You are a seasoned professional with a robust background in the design and verification of IP cores and/or SOC. You have a strong command of Verilog/System Verilog and are experienced in developing and managing testbenches in UVM environments. You are a natural leader with a proven track record of guiding and motivating teams to achieve their goals. Your expertise in memory protocols like HBM/DDR/LPDDR and familiarity with IP design and verification tools positions you as an invaluable asset to any team. Your problem-solving skills, coupled with your ability to communicate effectively, enable you to navigate complex technical challenges and deliver high-quality solutions. You thrive in dynamic, multi-site environments and are driven by a passion for continuous learning and growth. What You’ll Be Doing: Specify, design/architect, and implement IP Design and/or Verification environments for synthesizable DesignWare cores. Lead a team of 5 to 10 design and verification engineers, guiding them towards the closure of day-to-day design and/or verification activities. Work closely with RTL designers, Architects, and Verification Engineers as part of a global team. Understand design specifications and develop RTL code, test plans, and testbenches at both unit and system levels. Ensure product release milestones are met through effective regression debug triaging and verification activities. Contribute to the development and implementation of NextGen DesignWare HBM IPs, fostering a culture of continuous improvement and innovation. The Impact You Will Have: Drive the successful design and verification of high-performance memory controller IPs, contributing to the advancement of cutting-edge technology. Ensure the timely and high-quality release of IP products that meet stringent industry standards. Enhance the efficiency and effectiveness of design and verification processes through leadership and technical expertise. Foster a collaborative and innovative team environment, enabling the professional growth and development of team members. Support the strategic goals of Synopsys by contributing to the development of industry-leading IP solutions. Strengthen Synopsys' reputation as a leader in the semiconductor industry through the delivery of high-quality, reliable products. What You’ll Need: BS/MS in EE/EC/VLSI with 10-15 years of relevant experience in the verification of IP cores and/or SOC. Experience in leading a team of engineers and guiding them towards achieving project milestones. Hands-on experience in RTL design and/or verification of complex designs at the IP or SoC level. Strong knowledge of Verilog/System Verilog and experience in developing testbenches in UVM environments. Experience with memory protocols like HBM/DDR/LPDDR and familiarity with IP design and verification tools. Proficiency in Perl/Python-based automation and excellent communication and problem-solving skills. Who You Are: A strong team leader and motivator with a go-getter attitude. A technical contributor with expertise in System Verilog/Verilog RTL coding and testbench development. Capable of creating deliverables that meet high standards without requiring close supervision. Skilled in understanding design and verification milestones and aligning team tasks accordingly. Experienced in improving coverage metrics and defining additional test cases. Familiar with HDLs such as Verilog and scripting languages like shell/Perl/Python. A good team player with strong interpersonal and communication skills. Highly motivated and self-propelled, thriving in a project and team-oriented environment.

You Are: You are a highly motivated and experienced Applications Engineer with a passion for cutting-edge technology. With at least 5 years of experience in design, verification, or applications, you bring a wealth of knowledge in ASIC Front-End development. Your strong analytical, reasoning, and problem-solving skills enable you to tackle complex technical challenges head-on. You have a keen eye for detail and a high degree of self-motivation, driving you to excel in your work. Your exceptional verbal and written communication skills allow you to effectively collaborate with customers and internal teams. You are excited about working with Synopsys' Security IPs (Crypto IPs, Interface Security, Root of Trust, etc.) and the latest industry specifications/applications on various hot market segments. You are ready to provide Security IP integration guidance to customers throughout their SoC flow and support silicon/system bring-up. Some travel is required for this role, and you are comfortable with that. What You’ll Be Doing: • Understanding Security IP applications on customer-specific SoC and systems. • Staying abreast of the latest ASIC/SoC design flows and EDA tools. • Providing expert advice and support to configure and resolve Security IP integration challenges, including configuration, validation, synthesis, floorplan, STA, DFT, silicon bring-up, etc. • Conducting integration training for customers and reviewing their major SoC milestones. • Collaborating with R&D to produce application notes on advanced topics. • Providing pre-sales support on Security IP integration and supporting conference demos. • Giving feedback to Synopsys R&D for continuous Security IP product improvements. • Participating in R&D design reviews to align development with future customer needs. The Impact You Will Have: • Enhancing customer satisfaction by providing expert guidance and resolving technical challenges. • Driving the successful integration of Security IP into customer SoC systems, leading to innovative next-generation products. • Contributing to the development of advanced applications that benefit the wider engineering community. • Supporting pre-sales activities to help secure new business opportunities for Synopsys. • Providing valuable feedback to R&D, contributing to the continuous improvement of Synopsys' Security IP products. • Playing a key role in silicon/system bring-up, ensuring successful deployment of Synopsys technology. What You’ll Need: • Bachelor's and/or Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields. • At least 5 years of experience in design, verification, or applications. • Skills in cryptographic algorithm implementations and related security algorithms (e.g. hashing, symmetric ciphers (AES), public key cryptography (RSA, ECC), MACSec). • Hands-on experience with ASIC Front-End development. • Strong analytical, reasoning, and problem-solving skills. • Excellent verbal and written communication skills. Who You Are: • Detail-oriented and self-motivated. • Possess strong problem-solving abilities. • Effective communicator with both technical and non-technical stakeholders. • Team player who thrives in a collaborative environment. • Adaptable and able to handle multiple tasks simultaneously. • Passionate about continuous learning and staying updated with industry trends. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on integrating leading-edge Security IP (SecIP) into ASIC SoC/systems for next-generation products. Our team collaborates closely with customers to provide Security IP integration guidance and support throughout their SoC flow. We work on the latest industry specifications/applications and contribute to the continuous improvement of Synopsys' Security IP products.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced engineer with a solid background in electrical or electronic engineering, computer engineering, or computer science. You thrive in dynamic environments and are adept at managing multiple tasks concurrently. With at least 3 years of experience in IP and/or ASIC Design/Verification/Applications, you are proficient in RTL coding in Verilog, simulation, synthesis, and static timing check. Your domain knowledge in PCI Express, CXL, and Ethernet protocols sets you apart. You possess excellent verbal and written communication skills in English, enabling you to interact effectively with customers. Your creativity and problem-solving skills are exceptional, and you are always looking for ways to innovate and improve efficiency. Self-motivated and responsible, you take ownership of your work and deliver high-quality results. What You’ll Be Doing: • Engaging in the entire SOC design flow from architecture to mass production silicon debug. • Collaborating closely with customers to understand their needs and customization requests. • Providing integration training to customers and reviewing their major SoC milestones. • Offering feedback to Synopsys R&D for product improvements and customization features. • Participating in IIP design reviews to align development with future customer needs. • Developing innovative tools to simplify daily tasks and improve efficiency. • Authoring application notes for gate-level simulation, silicon debug, and physical implementation. The Impact You Will Have: • Enhancing customer satisfaction through effective support and training. • Contributing to the successful integration of Synopsys' IIP into customer products. • Driving continuous improvement and innovation in Synopsys' high-speed interface IP offerings. • Ensuring the reliability and performance of customer SoCs through rigorous testing and validation. • Facilitating smooth silicon bring-up and mass production for customer products. • Helping Synopsys maintain its leadership position in the semiconductor industry through your expertise and dedication. What You’ll Need: • Bachelor’s and/or master’s degree in Electrical and/or Electronic Engineering, Computer Engineering, or Computer Science. • Minimum 3 years of IP and/or ASIC Design/Verification/Applications experience. • Hands-on experience with RTL coding in Verilog, simulation, synthesis, static timing check, equivalence check, etc. • Domain knowledge of PCI Express, CXL, and Ethernet protocols. • Good verbal and written communication skills in English and the ability to interact with customers. Who You Are: • Creative and results-oriented with the ability to manage multiple tasks concurrently. • Highly motivated and responsible, with a strong sense of ownership in your work. • Excellent problem-solving skills and attention to detail. • Adaptable and eager to learn new technologies and methodologies.

**重要**請務必投遞履歷至官網，連結如下 https://careers.synopsys.com/job/hsinchu/solutions-engineering-staff-engineer/44408/75484659232 As a Solution Engineer for the Synopsys Custom Designer product, you will enable customer flows and deploy Custom Design solutions for key customers. You will collaborate with R&D to define and drive the product direction by identifying designer needs and specifying tool capabilities for the next generation designs. You will be responsible to define the methodology, develop training, address customer issues, and provide experienced help to the Field. In addition, you will drive the requirements specifications and work closely with R&D on early-stage new feature development. ● BSEE/MSEE with 5+ years as a Design engineer and/or a CAD engineer working as part of a Custom IC Design team. ● Knowledge of the complete custom/mixed-signal design flow, custom and analog layout design is required. ● Familiarity with 3DIC, Custom IC core applications like Schematic-Drive Layout (SDL), Analog Placement and Routing, LVS/DRC, Extraction and Analog/Digital Co-design and Simulation Analysis is desired. ● Scripting skills (TCL, Perl, Python) required. Good communication skills and the ability to interface with customers are essential. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is self-supporting and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job. Manages both pre-sale and post-sale technical staff and support activities including assessment of how company products meet customer needs and the preparation of product specifications for development and installation of customized applications/solutions. May provide pre-sale technical support in sales presentations and product demonstrations. Establishes and maintains lines of communication with design engineering on issues such as considerations for product reliability. Works with marketing and product managers to define new products and may provide insight from the field back to these groups. Selects, develops, and evaluates personnel to ensure the efficient operation of the function.

請務必透過官網投遞履歷: https://careers.synopsys.com/job/hsinchu/asic-digital-design-engineer-sr-engineer/44408/70723117808 【Job Description】 The selected candidate will be a supervised contributor of Synopsys DesignWare Processor team involving in development of leading edge DesignWare processor IP products such as HPC processors, NN accelerators, vision processors, as well as energy-efficient processors. The responsibility is to complete assignments meeting quality of result targets under appropriate supervision. The assignments could be applied to architecture, micro-architecture, performance analysis, logic design, verification and validation operations, as well as related engineering flows or environments and necessary signoff delivery processes. Depending on individual’s capability and career development, the works may include but not limited to investigation, creation, implementation, analysis, debugging, and optimization in said areas. In addition, the candidate would have great opportunities to collaborate with cross-team or cross-site colleagues on various technical matters such as algorithms, methodologies, quality of delivery, SoC prototyping, system bring-up, or any other engineering works that are required for overall business operations. 【Job Requirements】 •Master degree in EE or CS related engineering major is required as a minimum from reputed colleges •Minimum 0 to 3 years of experience in in modeling, benchmarking, or profiling for processors or similar compute engines, or related digital frontend design or verification for IP business •Comprehensive knowledge in software engineering, microprocessor architecture, memory architecture, or system architecture •In-depth hands-on experiences in architecture, micro-architecture and RTL design, or functional and performance modeling, performance profiling, performance benchmarking, or simulation verification based on UVM with co-simulation, regression flows/environments and respective debugging activities, plus authorship of technical specs •Programming skills: C/C++, Python, SystemVerilog, SystemVerilog Assertion, Verilog, shell scripts, or assembly •Tools for functional formal, functional coverage, teamwork collaboration (continuous integration, source control management, issue tracking, etc.), ADL-based generation (such as Synopsys ASIP Designer), or software toolchains •Experience with multi-site development is helpful •Written and Verbal communication skills: -Creation, modification and review of documentation: design or verification work plans, engineering quality processes, test scenarios, test reports -Ability to profile the values, requirements, issues, risks, and solutions for engineering works presentation and persuade and compromise for consensus -Ability to follow disciplines describing issues and changes in track systems •Analytical skills: -Analysis of signoff requirements for product releases -Ability to analyze QoR and verification results for major milestone reviews and assessments. •Self-motivated team player with leadership, be able to thrive in a fast-paced engineering environment •Ability to motivate, and influence team members toward desired results is a plus

請務必透過官網投遞履歷: https://careers.synopsys.com/ Job description: We’re looking for a Application Engineer for top-tier foundry and key customer support, focusing on physical verification (DRC/LVS/PERC/Fill), product validation (Quality Assurance) and signoff solution enablement. In this role, you will learn and apply knowledge in areas of SoC physical design enablement, advance process effect, analysis and signoff. Primary Responsibilities include: * Work closely with top-tier foundry and key fabless company to deliver the most advanced physical verification solutions * Involve developing foundry process design kit (PDK) and validation methodology, working closely with R&D to develop methodologies to solve customer problems and to improve Synopsys tools and flows * Work with product-level R&D to drive new and improved technologies, methodologies and tool capabilities, and share and align on best practices. * Coordinate with and develop solid relationships with product R&D, end-user, and product manager Key Qualifications: * BS or MS degree in Electronic Engineering, Computer Science or similar. * Proficiency with at least one programming languages like Python, Tcl, Perl. * Experience with UNIX/Linux environment. * Familiarity with physical verification flows like DRC/LVS/PERC/FILL/DFM. * Understanding of complex layout/electrical design rules and layout of complex semiconductor devices would be a plus. * Prior knowledge and experience of tool/runset development/support is a plus. * Exceptional desire to learn, explore new technologies and demonstrate good investigation and problem-solving skills. * Capability to produce adequate technical documentation. * Has good communication skills and builds productive internal/external working relationships.