智邦科技股份有限公司

一、工作內容： 1.考勤管理 (含年度設定、行事曆規劃、排班調班、稽核協助與資料提供、系統優化等) 2.假勤處理 (含假單簽核、天災假/特殊假處理、每月假勤結算、問題回覆與排除等) 3.行政業務 (含白領外籍人士工作聘雇申請、居留證申請、越南簽證申請、在職證明製作等) 4.留職停薪作業 5.其他主管交辦事項

1. 規劃與執行人員招募、甄選、任用、報到及離職等相關活動 2. 校園合作案開發、實習計畫推動與校園關係維持 3. 組織異動作業 4. 維護與彙整人力資源資料及報表 5. 依據勞動相關法令，修訂公司規章 6. 研發替代役相關作業 7. 內、外部稽核窗口 8. 主管交辦事項

1.智邦學院核心人才培育課程開發、規劃與推動，包含主管訓/語言/AI智慧人才學習地圖/工作效率提升 2.協同人資發展課規劃教育訓練分配之業務及各項專案企劃與執行。 3.推動企業學習型文化塑造專案 4.雇主品牌社群平台經營維護管理事務 5.支援廠端國內、外客戶稽核(與訓練相關) 6.擔任內部講師，推動內部數位學習課程 7.公司內部定期電子月刊編輯發行 8.訓練數據分析 9.主管交代事項 備註:視人力調配狀況，偶爾需要跨廠支援支援新竹分公司(新竹市研新三路1號)或是竹南廠(苗栗縣竹南鎮科義街1號)工作項目，可搭廠區往返

實習期間:2024~2025(為期一年) 實習天數:至少一周三天(全天) 實習內容: 1.執行新人報到/訓練課程執行 2.協助招募/面試/徵才活動執行與例行性事務作業 3.其他日常行政/主管交辦事項處理 4.年度人力資源發展目標之專案創發與支援 備註:視人力調配狀況，偶爾需要跨廠支援支援新竹分公司(新竹市研新三路1號)或是竹南廠(苗栗縣竹南鎮科義街1號)工作項目，可搭廠區往返

1. 協助招募、訓練業務等相關活動 2. 校園關係經營-E-DM設計與寄發、重點系所窗口資訊建檔、社群媒體經營與宣傳 3. 支援年度校園徵才專案籌備與執行 4. 人事資料建檔與歸檔作業 5. 識別證製作與前置作業 6. 行政文書行政作業 7. 主管交辦事項 備註:視人力調配狀況，偶爾需要跨廠支援支援總部(新竹縣竹北市智慧一路1號)或是竹南廠(苗栗縣竹南鎮科義街1號)工作項目，可搭廠區往返

主要工作: 1.負責新產品在研發與生產間的橋樑 1-1.新產品DFM 的確認 (allegro ,Valor ,Tebo) 1-2.新產品試產的人,機,料,法,環 確認與準備(ISO,IPC/JEDEC,IEC) 1-3.試產問題的反饋,解決與追蹤 (SMT, Dip ,Press-fit ,Assemble ,testing ,packing) 2.新零件新製程技術開發與導入 2-1.協助供應商開發符合規範之零件並導入生產. 2-2.研究與發展 新製程,新材料,新設備 等之應用 並導入生產. 次要工作: -主管交付任務與議題 - 週報,月報,年報

Main JD: - New project hardware design - Current project maintenance, support and debugging - Review spec/test plan documents - Handle project as project lead to communicate with customers - Co-work with SI/Thermal/ME/EMC/ENV/IEEE team - Other MFG task support

工作內容: Main JD 主要工作內容: 1.System board bring-up/diagnostic application for timing relative chip of switch 2.Co-working with cross-functional teams on projects. Secondary JD 次要工作內容: 1.time synchronization application of 5G network development, includes IEEE 1588 PTP/SyncE *本職缺有出差需求，能接受短期1~3個月出差情形*(面試詳談)

1. Qualifications: a. Top expertise in signal integrity analysis with HFSS, SIwave, ADS, HyperLynx, Memory Designer, COM analysis and Matlab scripts. b. Top expertise in power integrity analysis with PowerDC, OptimizePI, PowerSI, or HSPICE. c. Excellent communicator specifically interfacing with hyperscale data center customers. d. Self-starter, self-motivated, self-actualized, and highly accountable with strong communication skills e. A good team player in working with customers as well as cross-functional teams. f. Master’s degree with 6 years SI PI work experience is a minimum, 10+ years work experience or PhD in signal integrity/power integrity is a plus. g. Experienced in SI PI automation tool development with Python or PyAEDT is a plus. h. Experienced in PNA/ENA measurement with micro-probing is a plus. 2. Responsibilities: a. Signal integrity frequency domain and time domain analysis for 56G/112G PAM4 and above including IL, RL, crosstalk, TDR impedance, eye diagram, BER, COM, ERL, VEC, VEO, ILD, ICN on overall PCB channels with ASIC models including TX FIR , RX CTLE, DFE, FFE at a system level. b. PI DC analysis, power/ground planes design, pre-layout floor planning, post-layout optimization, and troubleshooting. c. PI AC impedance analysis, PDN decoupling capacitors design, optimization, analog power filtering for ASICs, transient analysis including CPM, and troubleshooting. d. All SI/PI aspects of high-speed serial channels and DDRx SI analysis such as ASIC breakouts/fanouts, connectors, cables, including crosstalk, reflections, setup and hold timings, and other issues including understanding of PCB fabrication rules and tolerances. e. All aspects of high-speed serial channel link training, including thorough understanding of the applicable standard. This would involve working closely with the ASIC vendor to help them understand Accton’s design and channel models.

Main JD: 1. For specific projects, do diagnostic tools development, 2. For all projects, design automation for testing and cost down. 3. Support factory side for production (no matter EVT/DVT/PVT/MP...) 4. With the capability to communicate with customers and lead Accton internal SW RD team members. 5. Co-work with customers for the diagnostic development Secondary Job Description: 1. Documentize project SW design spec, SW user guide, 2. Support factory-side issues.

1. System board bring-up activity for staged prototypes, such as BSP bring-up for networking SoC 2. System board diagnostic (DIAG) software development for board validation in manufacturing 3.Coding for required application feature in diagnostic (DIAG) software 4. Co-working with cross-functional teams on projects. 5. Troubleshooting for software issues on system boards.

1. Placement 2. Routing 3. Constraint setting 4. Valor Check 5. Gerber out 6. To handle related working documents and processes. 7. To share the PCB layout know-how to the team. 8. To join the improvement activity of the PCB layout process. 9. Tasks from direct managers. ※視專業能力需求，必要時須先至新竹/台中受訓，完成後於約定工作地上班。

<依據學經歷核敘工程師級別> Junior工作內容: 1. Circuit Design 2. Layout Check 3. Debug and Test 4. Create Test Plan 5. Proposal and H/W Spec prepare 6. Create BOM 7. Material prepare 8. Create Part number Senior工作內容: 1. Become a project leader to lead team member 2. Training course for issues 3. Co-work with SI/Thermal/ME/EMC/ENV/IEEE team 4. Design Review check 5. To do communication with customer

Main JD 主要工作內容: 1.FPGA / CPLD RTL coding 2.Help HW platform design and test 3.System integrated test 4.New Platform survey, develop and test Secondary JD 次要工作內容: 1.Co-work with S/W to bring up platform and debug 2.Support production line Other requirement 1) Interest RTL 2) Able to understand design spec. and define/design the IP 3) Have FPGA/CPLD verification, HW debug experience 4) Familiar with I2C/UART/SPI/PCIe protocol is plus 5) Familiar with scripting language is plus (shell script/python ...etc)

Main JD: 1. Explore/Develop New Technology 2. Circuit Design 3. Layout Design 4. Debug and Test 5. Create Test Plan and Test report 6. Proposal and H/W Spec design Second JD: 1. Create BOM 2. Material prepare 3. Create Part number 4. Component sourcing

1. Become a project leader to lead team member 2. Training course for issues 3. Co-work with SI/Thermal/ME/EMC/ENV/IEEE team 4. Design Review check 5. To do communication with customer

1. To learn Orcad and use it for circuit design and to use allergo to check layout file 2. To study data sheet/reference design to apply circuit 3. To come out design guide for layout and test plan for testing 4. Debug for issues relative design 5. Co-work with SI/Thermal/ME/EMC/ENV/IEEE team 6. Solder passive component and ASIC

1.HW design & validation of Timing Switch ( 1PPS) . 2.HW design , debugging and testing of 400G Ethernet switch. 3.High speed Ethernet switch design . 4. HW circuit design, Layout review, BOM, HW testing & debugging . 5. SI/PI simulation basics , scripting language, FPGA,CPLD experience.

1. 網通產品研發。 2. 產品驗證和測試。 3. 協助工廠解決生產問題。 4. 擔任RD負責解決project所有問題。

1.設計開發與驗證產品 2.將產品導入MP與協助分析生產問題 <請留意>: 面試地點安排於竹北企業總部