鑫創科技股份有限公司

1.工作內容:USB or SATA or PCIE related IP maintenance & development 2.具備以下相關經驗佳(無經驗可培訓): 2-1.Cell-base IC design flow 2-2.RTL(Verilog), Synthesis(DC), prime_time 2-3.CIC下線經驗

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

1. firmware debug and coding 2. 維護已開發產品的firmware、測試/驗證工具 3. 協助NAND Flash特性測試/分析、FPGA驗證 4. NAND sorting程式維護與開發

1. Preamp/ Sigma delta ADC/Logic control/circuit design and simulation. 2. Co-work with Layout engineer. 3. Layout plan. 4. 大學或研究所修過電子學，有Analog circuit design或spice simulation經驗者佳.

1. Handle customer complaints/ return/ failure analysis/ improvement. 2. Facilitate 8D process and release final report. 3. Coordinate customer audits and follow-up activities. 4. Communicate questionnaire from the customer into the appropriate channels. 5. Participating in teams to help make necessary improvements and changes to all process related issues. 6. Supplier management including product yield monitoring, quality abnormality issue handling/ process audit and drives closure on improvement action. 7. Participating in teams to help make necessary improvements and changes to all process related issues. 8. ISO 9001 QMS lead auditor or CQE/CQT certification is a plus.

具以下相關經驗者佳: 1. DRAM layout 2. TSV layout 3. DRAM Sub-WL driver layout 4. DRAM Sense amplifier layout 5. DRAM IO layout 6. DRAM power bus IR 及 EM 7. DRAM full chip floor plan

1.計算BL length與parasitic capacitance 对 loading及couple effect的影響 2.建Array model及simulation 3.計算sense margin 4.具以下設計經驗者佳: (1). DRAM Array設計 (2). DRAM WL driver 及 Sub-WL driver (3). DRAM BG control設計，調WLon to SA timing, SA to WLoff timing, tRP/tRCD/tWR等 Array相關timing (4). WL decoder, WL redundancy (5). Sense amplifier (6). OCSA (offset cancelling sense amplifier)

1.計算WL Ioff對cell leakage及refresh time interval的影響 2.Self refresh counter及control design 3.具以下設計經驗者佳: (1). Main WL, Sub-WL (2). DRAM WL driver及Sub-WL driver (3). DRAM BG control,调 WLon to SA timing, SA to WLoff timing, tRP/tRCD/tWR等 Array相關timing (4). WL decoder, WL redundancy

1. YSEL 及 Pre-fetch design 2. SA 到 YSEL timing design 及 YSEL pulse width design 3. Data path serial-to-parallel 及 parallel-to-serial path design 4. Data path FIFO design 5. DLL design 6. Column repair design 7. CLK tree implementation design 8. 具Data path, SA設計，第一級sense amplifier經SW到LIO, MIO, DSA設計經驗

1. Receiver design 2. Output driver (TX) design 3. ZQ calibration design 4. RX DFE/CTLE design 5. DQS latch DQ path design 6. ODT design

1. DFT (design for test) design, CPTM design 2. MBIST design 3. Array test mode design, array timing TM 4. Analog (pumping) test mode design, voltage regulator TM 5. TSV test design 6. IEEE 1500 design (WIR, WSI, WSO) 7. IO loopback test design 8. Data path MISR design

1. Hamming code ECC design 2. RS code ECC design 3. ECS design 4. SEV design

1. Pumping design 2. Regulator design 3. Temperature design 4. OSC process monitor design

1. AWORD design 2. DWORD design 3. MISR design 4. Native path design 5. DAPR/APAR/AERR/DERR design 6. IEEE 1500 design 7. TSV design 8. PHY design

1. Hard PPR design 2. Soft PPR design 3. Broadcast design 4. OTP design 5. OTP control design 6. Self repair design 7. Row repair design 8. Column repair design

1. MEMS and MEMS application Product Planning 2. Product Overall Schedule Control 3. Strategic Customers Promotion & Contact Window 4. Verification Sample and Promotion Material Preparation 5. Host Information Update a. Regularly update host information and join related seminar. b. Competitor analysis c. Market analysis 6. Regular Bottom Price Settings