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[益華暑期實習計畫開跑囉] 一年一度的Cadence Summer Intern機會又來啦! 邀請想以C/C++/ Python/其他script language做軟體開發的同學，展現你/妳的專才技能! 實習時間: ．7/1~8/28 ．一周五天。 申請對象: 資工/電機/電子工程相關學系 在學或畢業之學生 Job Description: The intern software engineering position will support and improve the implementation the state of art extraction products in a fast-paced, small team environment. Experience in C/C++ coding, with EDA background is a big plus!

Essential: The position requires MSEE, or equivalent, with significant and deep industry experience in designing complex protocols and/or hardware systems. MUST have excellent communication skills with both written and spoken English. Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows. Must excel in and demonstrate solid debugging experience/skills. Emotionally intelligent collaborator and communicator. Experience with team-wide collaboration tools and processes. Drive and ability to schedule workload and plan own tasks effectively as well as coordinate with and adapt to other's needs and priorities when needful. Agile! Adaptive! Strongly recommended: Verification experience using Cadence simulation and/or emulation products is highly desired. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended. Experience in memory sub-system design and operation is strongly recommended.

Job description: This position is for an R&D engineer, who will be involved in developing Innovus Implementation System. The position involves interaction and collaboration with a highly motivated global R&D team. Essential Job Functions: You will be responsible for designing, developing, troubleshooting and debugging software programs in the areas of P&R. Work closely with product engineers/technical sales to provide engineering solutions and workarounds to make customers successful Minimum Qualifications: • Highly technical engineer with excellent problem solving skills • C/C++ software development experience in Linux environment • Strong understanding and extensive usage of data structures and algorithms • Great communication skills and a strong desire for working with customers • MS (Ph.D. track a plus) in Computer Science or Electrical Engineering. Preferred: • Knowledge of physical design algorithms,. • Prior R&D experience working on IC physical designs tools • Hands on experience using the above physical design tools and knowledge of physical design flows a plus. • Experience with Tcl and other scripting languages

Job Description: This position is in Cadence Pegasus Physical Verification R&D team in Hsinchu, Taiwan. The candidate for this position will be developing design rule check (DRC) and FILL decks for advanced nodes of semiconductor manufacturing, The job involves creating quality check (QC) patterns, writing physical verification DRC and FILL rules and developing decks consisting of these rules. It also involves testing these decks on real customer designs and troubleshooting the deck and tool issues, providing feedback to Pegasus Foundry Team, Pegasus R&D, and foundry partners. Requirement: At least 2 years of previous experience with DRC or FILL deck development, and BS or MS degree in engineering.

We are looking for an R&D Software Engineer for our FastSPICE circuit simulation. Working within a world class engineering team, this position is responsible for participating and creating the state-of-the-art circuit simulation technologies and solutions. R&D in this position develops software according to specifications based on objectives and works within the parameters provided. Analyze and evaluate product issues and provide recommendations in productive ways within the general parameters under broad supervision. Analyze customers’ applications and propose implementation plans based on the general objectives and knowledge of overall architecture of cadence products. Position Requirements: - The candidate must have a strong software engineering background with good skills in C/C++ development in a Unix environment. - He/She must have a proven ability of quick self-learning and work with other engineering and cross-functional teams to deliver innovative technologies in a production environment. - Required education for this role is a BS in CS/EE/math/physics plus 4 years of experience in C/C++ and EDA experience/ Or MS in CS/EE/math/physics plus 2 years of experience in C/C++ and EDA experience. Fresh graduates with relevant backgrounds are also welcome to apply.

Position Description: The candidate will focus on Chip, IC Packaging, Board space and 3D-IC application development. The candidate will work with customers to deeply understand their requirements and discuss these with the factory to develop the required software. Preferred Qualifications: • Master's degree in Computer Science, Electrical Engineering, or a related field. • Experience in software performance, software capacity, software usability, or EDA software development. Position Requirements: • Programming language: Java (major), C/C++ (minor) • Common Skills: shell script, or Tcl script • Strong background in one of the following: - Database Optimization Development □ Focus Domain: Compiler, Computer Architecture, Database Theory, Virtual Machine. - Database Core Development □ Focus Domain: Database Theory, Information Theory, Information Security. - Design Rule Development □ Focus Domain: Computational Geometry, Linear Algebra, Calculus. - Software Quality Development □ Focus Domain: Software Testing, Compiler, Programming Language Design. - Data Processing Development □ Focus Domain: Parallel Programming, Compiler, User Interface Design, Computer Graphics. - EDA functionality development □ Focus Domain: Design Flow Automation, Software Integration • Knowledgeable in UNIX and Windows • Knowledgeable in Electronic Device Nomenclature • Ability to work individually or with a small distributed team • Ability to interact professionally with the customer • Ability to profile the values, requirements, issues, and risks. • Ability to communicate in English.

Job description: • Drive key customer engagements success and deliver good quality solution on time. • Regularly join customer meetings and communication to well conscious project requirement and meet expectation. • Work closely with multiple RD/PE teams to drive and influence product development to fulfill customer requirements. • Manage beta programs, author documentation and track customer issues. • New advanced feature verification, customer trainings Job Requirements: • Candidate must have 5+ years relevant industry experience with a MSEE -or- 7+ years’ experience with a BSEE. • In-depth knowledge & industry experience in signal/power integrity(SI/PI) analysis for IC package and PCB designs with Sigrity PowerSI, SystemSI, Clarity, etc. • Basic perl, python coding capability for analysis flow automation for Sigrity Tools • Patient to listen feedback and has strong technical insight to identify the root cause. • Good oral and written communication skills on Chinese and English

Job Description We are seeking a talented individual who will participate Virtuoso PDK (Process Design Kit ) development, quality and PDK applications related projects with leading foundry. This position will support Virtuoso PDK quality delivery, SKILL programming in task delivery, also provide PDK applications related support and interact with customers to overcome challenge in a fact-pace environment. Position Requirements: • MS degree in Electrical Engineering, Computer Engineering or similar areas. • Experience in analog design flow support or PDK delivery. • Knowledge and experience with analog design layout/simulation/digital/analog IC design flow, with layout domain knowledge would be a plus. • Experience in Linux shell environment and script programming, such as Perl and Tcl preferred. • Good communication skills in English. • Desire to learn, to take the challenge and to be a team player.

Position Description Developing precise test cases for DRC rules based on foundry decks with good quality by Virtuoso Working closely with PE and R&D for new features/enhancements of Pegasus DRC/FILL/LVS/PERC including deck coding/QC pattern generation Assuring the quality of physical validation tool Pegasus by analyzing existing test suites Validating code changes and integrating customer cases as part of regression test suite Requirements Good at Virtuoso for simple pattern creation (familiar with SKILL is a plus) With experience in developing and supporting physical verification activities in DRC/FILL area Solid knowledge of foundry layout rules and device identification concepts Working experience with UNIX and knowledge for shell/tcl scripting languages (familiar with Perl and/or python is a plus) Should be able to work independently and have adequate personality & communication skills to cooperate with cross functional groups

Responsibilities: 1. Grow Digital and Verification solutions business from key account 2. Develop account strategy 3. Build partnership with key decision makers Requirements: 1. Strategic thinking 2. Can do attitude 3. Strong communication skills 4. Electric Engineering background is a plus

The Circuit Simulation Developer is responsible for designing, implementing, and maintaining software designed to perform transistor-level VLSI circuit simulation. The ideal candidate would have expertise in device modeling and numerical techniques for VLSI circuit simulation. Understanding of analog/RF/mixed-signal IC design and verification practices is a strong plus. Candidate should have an advanced degree in electrical engineering, computer science, applied mathematics, or similar. Candidate should be proficient in C/C++ development. Demonstrated software engineering skills, with a good understanding of the efficient implementation of high-performance numerical algorithms and associated data structure design, and experience in relevant software frameworks is a plus. Candidates with experience in related fields will be considered, particularly: 1. Transistor-level time-/frequency-domain SPICE and RF analysis algorithms 2. Parasitic linear network reduction and analysis algorithms 3. Statistical analysis, reliability aging analysis, EMIR analysis, electro-thermal analysis, circuit check algorithms 4. Device physics, compact device modeling, behavioral modeling, statistical modeling, reliability modeling 5. Numerical analysis, especially numerical linear algebra, sparse matrix techniques, or numerical methods for the solution of ordinary and partial differential equations 6. High-performance computing / large scale scientific computing and deployment of parallel numerical algorithms

The Cadence Protium team is looking for talented software engneer to join and contribute to our Protium compiler router development. You’ll have a great opportunity to make a difference by applying your engineering and team collaboration skills to optimize the compiler for compile time, fclk performance and memory efficiency. Requirements · MS with 3+ years or PhD with 2+ years in engineering, computer science or related field. · Strong understanding of data structures, algorithms and databases. · Demonstrated proficiency in C++, gdb debugging, and general software development skills

Position Description • Physical implement the high-performance core with the foundry advanced process technologies • Collaborate with R&D to deliver high quality Innovus solutions to customers • Provide technical support in Cadence Innovus platform • Seek solutions to address tool and flow issues proactively • Will be a key contributor to customers’ success Position Requirements • APR expertise from Floorplan to GDS tape out over 7 years - Real tape out experiences is the MUST - ASIC design flow customization and development/tape out • Being familiar with Cadence Digital Design Innovus Platform will be much preferred • Effective inter-personal communication and analytical skills are essential • Good command of oral and written English is required • Passion, teamwork, and customer focus • “Can-Do” attitude

Position Description • Develop PEGASUS/PVS DRC, FILL, LVS, LPE rule decks and RCX flow for worldwide foundries. • Manage onsite technical qualification to ensure both PEGASUS/PVS decks and tools are officially qualified by foundries. • Collaborate closely with early adoption customers to track and resolve product issues • Establish communication channels with R&D to capture customer needs and requirement spec. • Work with R&D to enhance and improve PEGASUS/PVS, positioning it as a leading edge Physical Verification tool Position Requirements • B.S. in Electrical Engineering (EE), Computer Science (CS), or related area (or equivalent) and 3 - 5 years of experience with Physical Verification tool support/development OR • M.S. in EE or CS, or related area (or equivalent) and 1 - 3 years of experience with Physical Verification tool support/development • Profound knowledge with Foundry Design Rules and semiconductor fabrication process • Ability to develop PEGASUS/PVS rule deck for worldwide foundries, ensuring quality, performance, and compliance with schedules and qualification requirements. • Proficiency in TCL and PERL scripting is required • Strong English communication skills. • Software development experience preferred; familiarity with Cadence SKILL programming is a plus. • Experience with IC design and CAD support is advantageous.

This position is for an R&D engineer, who will be involved in developing Innovus Implementation System. The position involves interaction and collaboration with a highly motivated global R&D team. Essential Job Functions: The candidate will be responsible for designing, developing, troubleshooting and debugging software programs in the areas of P&R. Work closely with product engineers/technical sales to provide engineering solutions and workarounds to make customers successful Minimum Qualifications: Highly technical engineer with excellent problem solving skills C/C++ software development experience in Linux environment Strong understanding and extensive usage of data structures and algorithms Great communication skills and a strong desire for working with customers MS in Computer Science or Electrical Engineering. Preferred: Knowledge of physical design algorithms,. Prior R&D experience working on IC physical designs tools Hands on experience using the above physical design tools and knowledge of physical design flows a plus. Experience with Tcl and other scripting languages

The Jasper engineering team is seeking a Product Engineer to help drive the industry’s leading formal verification tool. The Product Engineer (PE) bridges the gap between customers, R&D, and field Application Engineers (AEs). In this highly creative and innovative role, they are responsible for ensuring that existing flows and apps meet the ongoing needs of our customers, while also developing flows and requirements to solve new verification challenges. The PE will collaborate closely with both customers and R&D to drive specification, implementation, and evaluation/benchmarking of the new solutions. In addition, the PE will be responsible for the roll-out of new features to AEs and customers, and in some cases will play a pivotal role performing hands on work, (remote or onsite) to enable key customers to achieve their verification goals with very high performance & efficiency. This position gives abundant exposure to work on and influence the latest design styles and verification methodologies that are used by large semiconductor companies. This job may occasionally involve worldwide travel to attend meetings or conferences, or to assist with product demonstrations and evaluations at customer sites. Desired Skills and Experience • The candidate should possess minimum BE/B. Tech engineering in CS or EE with minimum 8 years of industry experience. • A general understanding of Assertion Based Verification (ABV) is a must. • Hands on experience with using a formal property verification tool such as Jasper is a must. • Hands on design experience using Verilog, System Verilog, VHDL is a must. • Understanding of the differences between synthesizable vs non-synthesizable coding styles is a must. • Hands on experience using an HDL simulator such as Xcelium or Incisive etc. is a plus. • Knowledge or experience with high level modeling languages such as SystemC is a plus. • Hands on experience with common scripting languages such as Python, TCL, sh etc. is a must. • Knowledge of Verification IP and common protocols such as AMBA is a plus. • Knowledge of sign-off methodologies using code & functional coverage is a plus. • Highly technical & hands on engineer with an ability to partner with key customers and provide expert support to field application engineers. • Travel will be required to visit Cadence sites and/or work at customer sites • Highly organized, self-motivated individual with demonstrated ability to multi-task • Very good communication skills and a strong desire for working in a global environment with customers, developers, marketing and sales. • Passionate about adopting and promoting new technologies and making customers successful. • Successful in building and delivering training content on rolling out new products/methodologies

Position Description: 1. To provide key technical support in digital IC design synthesis products. 2. To demonstrate strong ability and to be hands-on in synthesis/DFT, and low power methodology. 3. To run benchmarks, characterize problems, and support key customer engagements. 4. To work with team, customer and R&D on new methodologies and flow refinement. Position Requirements: 1. Master with 3-5 years working experience or Bachelor with 7+ years’ experience in IC design. Cadence Genus experience will be a plus. 2. Understanding of synthesis/DFT techniques, constraint and timing analysis is required. Knowledge of power analysis & optimization will be a plus. 3. Experiences in synthesis/LEC/DFT/power analysis tools. 4. Advanced node experiences and familiar with APR tools will be a plus. 5. Good communication in English and Chinese, good confidence and good self-motivation. 6. Be familiar with shell/perl/tcl etc. script language.

Position Description: • Work closely with Sales team to identify and scope opportunities for Cadence Emulation and Prototyping products. • Plan, execute and manage key technical evaluations and benchmark with existing and potential customers. • Train, ramp-up and accompany customer project. • Conduct basic and advanced trainings, presentations and demos as necessary. • Providing technical expertise to address clients’ queries, which need expert involvement. • Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement. Position Requirements: • Minimum 3 years hands-on expertise on SoC design & verification technique • Design experience in Verilog/VHDL for IP or SoC chip level is required • Knowledge of System Verilog/VHDL and HDL simulators is required • Experience with hardware emulator or FPGA prototyping is a big advantage • Knowledge of Unix and Linux is highly desired • Familiar with shell/python/tcl etc. script language is a plus • Advanced Verification Methodology like UVM is a plus • Strong verbal and written communication skills in English • Strong teamwork skills with good human relationship • Ability to travel within Asia Pacific region for onsite customer visits is a plus.

Job Description: As a Verification IP Engineer for RSS Verification IP team, you will be expected or tanning to be an expert in a specific domain of Verification IP family- protocol and product-wise. The Application Engineer main role is to help accelerate VIP portfolio adoption at Cadence’s customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a VIP and protocol expert, the Application Engineer drives product knowledge transfer to customer, providing training and requirements collaterals. The Application Engineer is expected to collaborate with other team members (R&D, PE and support) to ensure the design is in line with the technical and quality requirements set for the customer’s requirement. Requirements and Qualifications: • BS/MS with Electrical engineering or Computer Science. • At least 3-5 years of experience with Verification or Design Experience. • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. • UVM based functional verification environment development is required. • Familiar with anyone kind of standard protocol is desirable. • Team orientation, mature work attitude, and good judgment under pressure. • Position requirements, propose solution, evaluate prototype flow and drive to success • Plan, execute and manage key technical evaluations and benchmarking • Conduct basic and advanced trainings, presentations and demos as necessary

Position Description -Responsible for the development of Pegasus, our next-generation massively parallel physical verification system, with focus on the Fill and DRC product development and foundry enablement. -Performs as individual contributor on case analysis, problem solving, validation and documentation. -Working closely with PE and QPV for the DRC/FILL deck developing and QC pattern generation. Requirements -Solid background in computational geometry and graph algorithm. -Excellent programming skill in C/C++/Python. -Some knowledge on the foundry qualification of EDA tool is preferred. -Good English reading and writing skills. -Good communication skills.