創意電子股份有限公司

Physical Design Staff ※ Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. 3. 3 years+ exp, have experiences in 16/12/7/5nm IC design experiences will be plus. Physical Design Manager/Technical Manager 1. Perform TOP or big-scale sub Top Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis 4. Be the block coordinator for a hierarchical design 5. Take responsibility for schedule control and awareness about critical issues 6. Training and coaching flash/junior engineers 7. 7 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus

※ Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. 3. Have experiences in 65/40/28nm IC design experiences will be plus.

Job Description & Requirement 1. Perform physical synthesis from RTL or gate-to-gate optimization 2. Take responsibility for netlist, SDC and design quality check with customer 3. Chip I/O arrangement and verification with in-house tool 4. Perform low power structure verification (UPF/CPF) 5. Perform power replay and power analysis 6. Review/check implementation quality in each design stage 7. Cooperate with P&R in timing analysis 8. Planning chip level STA (e.g. flatten, HyperScale) strategy and machine arrangement for big design 9. Perform MMMC timing closure and signoff check 10. Schedule and team resource management 11. 8 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus

Job Description & Requirement 1. Perform physical synthesis from RTL or gate-to-gate optimization 2. Take responsibility for netlist, SDC and design quality check with customer 3. Chip I/O arrangement and verification with in-house tool 4. Perform low power structure verification (UPF/CPF) 5. Perform power replay and power analysis 6. Review/check implementation quality in each design stage 7. Cooperate with P&R in timing analysis 8. Planning chip level STA (e.g. flatten, HyperScale) strategy and machine arrangement for big design 9. Perform MMMC timing closure and signoff check 10. Schedule and team resource management 11. 5 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus

Job Description & Requirement 1. Perform TOP or big-scale sub Top Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis 4. Be the block coordinator for a hierarchical design 5. Take responsibility for schedule control and awareness about critical issues 6. Training and coaching flash/junior engineers 7. 8 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus

Job Description & Requirement 1. Perform TOP or big-scale sub Top Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis 4. Be the block coordinator for a hierarchical design 5. Take responsibility for schedule control and awareness about critical issues 6. Training and coaching flash/junior engineers 7. 8 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus

※ Job Contents: - Block/Chip level DFT feature and architecture definition. - DFT specification generation and review with customer co-work. - Implement block/chip level DC/AC SCAN, BSD, MBIST, Memory Repair, System BIST and IP macro test. - Deliver quality DFT timing constraints and support BE team timing closure. - Do all verifications on DFT structures, and deliver quality production ATE patterns. - Support ATE bring-up, and debug the ATE patterns for production flow, DFT diagnosis for yield improvement. - Lead DFT implementation team to support projects and review with customers and outsourcing vendor - DFT resource and schedule planning - DFT negotiation with Pre-Sales Customer ※ Requirements: - More than 5 years project experience in DFT design implementation. - Hand-on experience in Synopsys (DFT Compiler/TetraMax/VCS) and Mentor (Tessent MBIST/Scan). - English communication skill. - DFT Lead Capability: DFT Planning, resource/schedule planning, communicating with customers and outsourcing vendor

GUC Mixed Signal Department ●符合以下經驗之一 1. PLL/DLL/VCO circuit design 2. ADC circuit design 3. DAC circuit design 4. High Speed SerDes circuit design 5. 熟Matlab佳 6. 熟mixed signal design flow佳(ex. Inductor extraction, RC extraction, mixed mode simulation)

Chip Application Front-End Staff ※ Job Contents: 1. Took responsibility of creating SDC for the complex SoC. 2. Took responsibility of timing analysis with customer. 3. Took responsibility of planning low-power structure and review flow (CPF/UPF). 4. Supported back-end team in post-layout timing closures 5. Supported project team in central tech-library management 6. Run EDA-Tool and GUC in-house design kit. ※ Requirements: 1. Familiar with ASIC Flow. 2. Understood SoC IO structure and experienced of integrating 3rd party IP. 3. Understood physical synthesis flow. 4. 3 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus Chip Application Front-End Manager/Technical Manager 1. Perform physical synthesis from RTL or gate-to-gate optimization 2. Take responsibility for netlist, SDC and design quality check with customer 3. Chip I/O arrangement and verification with in-house tool 4. Perform low power structure verification (UPF/CPF) 5. Perform power replay and power analysis 6. Review/check implementation quality in each design stage 7. Cooperate with P&R in timing analysis 8. Planning chip level STA (e.g. flatten, HyperScale) strategy and machine arrangement for big design 9. Perform MMMC timing closure and signoff check 10. Schedule and team resource management 11. 7 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus

※ Job Contents: 1. Responsible for physical design flow development including APR, IR, CTS, timing closure methodology development, flow automation 2. APR and physical verification flow/scripts/environment development for advanced process nodes and 2.5D/3D-IC 3. Project support/execution & collaboration with EDA vendors ※ Requirements: 1. Experience in APR, IR analysis, timing analysis, or physical verification DRC/LVS 2. Experience in physical design project execution 3. Familiar with Cadence Innovus or Synopsys ICC2/FC, RC extraction, timing analysis 4. Knowledge with script and programming (TCL/Perl/...) skills 5. Better to have 40/28/16nm IC design experiences

General Solution Architect / Execution PM ※Job Contents 1) Handle project execution & management for advanced ASIC chip from Netlist-in to GDSII tapeout and silicon bring-up at prototype stage. 2) Involve pre-sale activities, including tech capability promotion, process selection, IP selection, chip implementation tech proposal and SOW drafting. 3) Some business travel is expected. ※Requirements: 1) Background : SoC chip Implementation Project lead, Physical design lead, DFT design lead, or RTL chip integration lead. 2) Good communication and program management skill. 3) Familiar with ASIC design flow and TSMC advanced technology

※Job Contents: 1. New product introduction 2. Production yield and quality improvement ※Requirements: 1. In semiconductor filed >= 3years 2. Advanced technology process integration experience, with Product or Device engineering is plus 3. With basic wafer test concept

1. SoC/ASIC/Testchip & package architecture designs for high speed Analog/Serdes, D2D, and HBM2/3/4 integrations (Server, Networking, Wireless, AI, AR). 2. Execute SI/PI/EMC design-optimization for chip/package/system integration and electrical performance optimization, e.g., eye diagram, jitter, IR/EM, system-PI, cross-talk, and SSN/SSO. 3. Develop system integration design guidelines with SI/PI total solution for advanced packaging technologies (InFO/CoWoS/3D-IC). 4. Working as R&D with customers on technology competitive analyses, and develop chip/package/system technology road map for future productivity.

※Job Contents: 1.Took responsibility of creating SDC for the complex SoC. 2.Took responsibility of timing analysis with customer. 3.Took responsibility of planning low-power structure and review flow (CPF/UPF). 4.Supported back-end team in post-layout timing closures 5.Supported project team in central tech-library management 6.Run EDA-Tool and GUC in-house design kit. ※Requirements: 1.Familiar with ASIC Flow. 2.Understood physical synthesis flow.

※Job Contents: 1. Responsible for IC DFT design methodology development and project support. 2. Flow development for Memory BIST, Scan, Boundary Scan, ATPG and so on. 3. In house EDA utility development ※Requirements: 1. MS in Electronic engineer or Computer science 2. Experience in DFT flow development (Memory BIST/BISR, SCAN, Boundary Scan, ATPG, Logic BIST, etc) 3. Experience in low power flow development (UPF/CPF/low power check/PSO/DVFS, etc) 4. Post-silicon ATE debug/support experience 5. Proficient in Unix shell/Tcl/Perl and programming skills 6. Proficient in C/C++ and QT 7. 16nm/7nm IC design experiences is a plus

※ Job Contents: 1. Design verification 2. Generate models for PI/SI simulation (CPM/IBIS etc...) 3. Testchip testing 4. Edit testing program (python) ※ Requirements: 1. Familiar with lab equipment and bench testing methods. (must) 2. A good team player with a strong motivation to succeed. (must) 3. MSEE degree (better) 4. Proficient in analog/mixed-signal circuit design principles and techniques (better) 5. Skilled in designing high-speed analog circuits such as PLL, frequency synthesizer, TX/RX equalizer, and analog front-end. (better)

We are looking for 2D/2.5D/3D-IC thermal integrity design talent, who is well-experienced at thermal/mechanical design at standard package (HFCBGA/SiP) and advanced package (CoWoS/InFO/SoIC), for ASIC electronic system co-optimization. 1. Thermal modeling & hotspots simulation for whole system architecture, including SoC, APT, SBT, PCB, and heat dissipation modules. 2. Thermal models extraction and design-optimization at 2D/2.5D/3D-IC for tape-out/sign-off. 3. Support thermal issues & solutions development at CP / FT / Reliability system. 4. Design of experiments and correlation for thermal & mechanical designs at ASIC & Package. 5. Research on materials and advanced heat management solution & implementation.

※Job Contents: SoC/Subsystem design : Job includes spec study, architecting, RTL coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, STA and FPGA verification. ※Job Requirements: 1.MS or PhD degree in EE, CS, or relevant fields 2.Good at digital IC front-end design flow such as Verilog/VHDL RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA 3.Experience in chip integration or subsystem design 4.Familiar with shell scripts for design automation such as Perl language 5.Familiar with ARM CPU and bus fabric is a plus 6.Familiar with DDR, PCIe or USB is a plus 7.Fluent in English communication is a plus

※Job Contents: 1. From design IPDFT to production IP testing 2. Study IP spec. Plan IP testing solution, Test Circuit Insertion, Design/Implement/Verify in Netlist or RTL 3. RTL sim, Pre-Sim, Post-Sim & Design Debugging 4. STA Timing Constrains and Timing Closure with FE, BE Engineer 5. ATE Pattern Generation and Verification 6. ATE Bring-up and Mass Production Yield Improvement ※Requirements: 1. Good Understanding or Coding Skills in Verilog and SystemVerilog 2. Have Understanding or Experience in RTL Design 3. Have Gate-Level Simulation and Debug Experience 4. Have Experience in some IPs like EFUSE, TCAM, PVT, ADC, DAC, PLL, DLL, PCIE, DDR, SERDES, USB, HDMI, LVDS, SDIO, EMMC, 5. Have Experience in using Design Compiler, PrimeTime, VCS, LEC, Spyglass, PTPX, Verdi, and so on Good at Python, TCL, and Shell Scripts

※ Job Contents: - Block/Chip level DFT feature and architecture definition. - DFT specification generation and review with customer co-work. - Implement block/chip level DC/AC SCAN, BSD, MBIST, Memory Repair, System BIST and IP macro test. - Deliver quality DFT timing constraints and support BE team timing closure. - Do all verifications on DFT structures, and deliver quality production ATE patterns. - Support ATE bring-up, and debug the ATE patterns for production flow, DFT diagnosis for yield improvement. - Lead DFT implementation team to support projects and review with customers and outsourcing vendor - DFT resource and schedule planning - DFT negotiation with Pre-Sales Customer ※ Requirements: - More than 5 years project experience in DFT design implementation. - Hand-on experience in Synopsys (DFT Compiler/TetraMax/VCS) and Mentor (Tessent MBIST/Scan). - English communication skill. - DFT Lead Capability: DFT Planning, resource/schedule planning, communicating with customers and outsourcing vendor