Job Description :
1. Verilog/VHDL simulate and verify on Vivado.
2. Familiar with Xilinx/Microchip FPGA.
3. RF Transceiver Controlling Experience is better.
4. JESD/LVDS..etc High Speed Interface Design Experience is better.
5. Optimizing System Design Experience is better.
6. Communication/Radar Background is better
P.S.注重團隊合作與學習態度
歡迎有經驗者投遞