鯨鏈科技股份有限公司

1. 高速介面電路設計 2. 負責Serdes PHY Ex. MIPI/PCIE PHY的開發與維護工作 3. 類比IP設計(EQ, CDR, OP, OSC, Regulator, BandGap, ...) *備註：此職缺非研發替代役*

1. Architecture design, RTL coding, simulation, synthesis, LEC, STA 2. Digital front-end design flow *備註：此職缺非研發替代役*

1. Architecture design, RTL coding, simulation, synthesis, LEC, STA 2. EDA flow optimization *備註：此職缺非研發替代役*

1. RTL coding(IP development) and simulation 2. IP(SoC) integration and simulation 3. Perform front end design flow such as lint, synthesis, formality, and timing closure 4. Coordinate with other teams for owned design 5. Provide design documentation, description and information to asic team and other teams. Experienced on below items are plus: a. AMBA protocol b. Peripheral IP: uart, i2c, spi…etc c. Memory bank design d. Asynchronous design *備註：此職缺非研發替代役*

1. Soc top integration and simulation 2. Perform front end design flow such as lint, synthesis, formality, and timing closure 3. Coordinate with IP owners for top integration 4. Coordinate with front end and back end engineers for report analysis 5. Experienced on clock tree design, reset design, boot design are strong plus *備註：此職缺非研發替代役*

1. Maintain and support front end design flow framework such as lint, synthesis, formality, and timing closure 2. Coordinate with IP owners for front end implementation 3. Coordinate with front end engineers and back end engineers for report analysis 4. Perform critical module implementation if needed 5. Utility development *備註：此職缺非研發替代役*

1. DRAM subsystem integration and simulation 2. Perform front end design flow such as lint, synthesis, formality, and timing closure 3. Coordinate with other teams for all dram subsystem related issue 4. Provide design documentation, description and information to asic team and other teams and customers. 5. Mentoring junior team members Experienced on HBM is a plus. *備註：此職缺非研發替代役*

Design verification: 1. SoC test environment build up 2. SoC test plan delivery 3. SoC test pattern build up 4. Regular regression and test report generation 5. IP verification support *備註：此職缺非研發替代役*

1. Design and build the Al inference platform. 2. Design and debugging Retrieval Augmented Generation (RAG) models. 3. Participate in the entire development life cycle of the Al inference platform. 4. Collaborate with AI/LLM developers to integrate models into inference platform. *備註：此職缺非研發替代役*

1. Design and build Visual Studio Code(VS Code) extension for AI inference platform. 2. Design and build efficient and reusable web applications. 3. Participate in the entire development life cycle of the AI inference platform. 4. Collaborate with AI/LLM developers to integrate models into inference platform. *備註：此職缺非研發替代役*

1. Use Verilog/SystemVerilog languages to verify design at block level or full chip level 2. Verification plan creation and implementation(test environment setup, modeling, test-case development and execution), coverage analysis, and regression cleanup 3. Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment. *備註：此職缺非研發替代役*

1. RTL design and simulation 2. ASIC/SOC prototyping and Validation 3. FPGA synthesis and implem *備註：此職缺非研發替代役*

1. 高速, 高功率電源的多層電路板設計 2. Gerber File製作發行並且建置Layout環境及資料庫維護 3. 協助評估IC routing guideline, pinout 4. 負責專案開發Placement, Layout routing