台灣電子系統設計自動化股份有限公司

Dear All, we're hiring. You're very welcomed to join us to create a new world! TESDA 是一家快速成長的初創公司，正在尋找具有 5 年以上經驗的經理或處長和數名數位設計驗證工程師。 作為 TESDA 的設計驗證工程師，您將能夠接觸和驗證來自世界級公司的複雜SoC 設計，除了具有競爭力的薪資還有現金及股票分紅。 如果您正在尋找可以為個人職業和財務成長，提供巨大增長機會的職位以及工作與生活平衡，那麼 TESDA 就是您的理想之選！ ========== Job description ========== 1. Qt C++ for Simulation GUI 2. Write compiler and Parser for verilog and system verilog 3. Optimization for software architecture. 4. Responsible for designing, developing, and debugging on verification EDA (electronic design automation) tool for ESL/RTL SoC design. ======== Qualification ======== - Graduate school degree preferred, but not a must - Great understanding of algorithm. ========== Key Capabilities ========== Required: - Proven C++ and SW engineering skills; - Proven data structures and algorithm knowledge; Plus: - Proven SoC modeling and simulation knowledge; - Analytic thinking and SW debugging skills; - Hardware description language: SystemVerilog/Verilog

TESDA 是一家快速成長的初創公司，正在尋找具有 5 年以上經驗的經理或處長和數名數位設計驗證工程師。 作為 TESDA 的設計驗證工程師，您將能夠接觸和驗證來自世界級公司的複雜SoC 設計，除了具有競爭力的薪資還有現金及股票分紅。 如果您正在尋找可以為個人職業和財務成長，提供巨大增長機會的職位以及工作與生活平衡，那麼 TESDA 就是您的理想之選！ 1. Responsible for system-level design verification 2. Develop test plans, test platforms, test cases, reference models, coverage models, and regression suites 3. RTL simulation/function verification/fault debugging 4. Drive and achieve coverage closure 5. Familiar with ARM or RISC-V & AMBA bus protocol is a plus. 6 Familiar with SVA/UVM test platform framework is a plus

TESDA, a fast growing startup is looking for manager with 5+ years experience and 1~5 digital design verification engineers. As a design verification engineer at TESDA, you'll be able to access and verify the design and implementation of hugely complex SoC from world class companies,attractive package and stock options. If you are looking for a position that can offer huge growth opportunity for career and personal finance and work-life balance, TESDA is the place to be! What you are expected to do Understand the design and implementation, define the verification scope, develop the verification strategy and infrastructure. Verify digital designs of large SoCs using advanced verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards with coverage driven methodology. Write and execute test plan to verify a design in a timely manner. What We are looking for Bachelors, Masters Degree or Ph.D in Electrical Engineering or Computer Science or Computer Engineering or related majors. Background or interest in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog. Experience of random stimulus with functional coverage and assertion-based verification methodologies. Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug. At least 2 years of relevant experience, school or industry are OK. What others can make you an excellent fit Expertise in bus or interconnect protocols (e.g. AXI, AHB, APB) a big plus. Background in verifying complex ARM/RISC-V based system, understanding RTL designs, and have experience in modeling of digital circuits a big plus. SystemVerilog, SystemC, C/C++ programming language experience. Good debugging and analytical skills. An open mindset & dream to work in an open and lively environment!

1. 大學期間曾修讀下列學科, 學習成果佳 1a. 數位邏輯 1b. 微處理器 1c. 計算機組織 2. 具備基礎 SystemVerilog 知識 3. 具備基礎 AMBA (AXI/AHB/APB) 知識