智原科技股份有限公司

USB/SATA/PCI Express/Ethernet/VBO/MIPI相關高速混合訊號介面之數位IC設計

high resolution Delta-sigma codec (for audio , FNPLL , sensor )混合訊號介面之數位IC設計

1. 依標準規格或客製化開發數位IP 2. 維護IP並撰寫相關文件

PCIe/MIPI/USB/SATA 相關controller IP之數位設計

1. ASIC開發數位電路設計,協助客戶制定規格並提供技術協助 2. SoC硬體整合及驗證環境之研發與客戶服務

SerDes PHY Circuit Design: 1. SerDes RX design, include CTLE, PGA, DFE… 2. SerDes TX design, clock buffer distribution, TX driver 3. be familiar with SerDes system operation.

General OSC/PLL/DLL/SSCG/CDR design & production experience 1) LC-tank VCO design & production experience 2) CDR design & production experience

1) LC-tank VCO design 2) CDR design

1. USB2 HSTX/HSRX/PLL design 2. USB3 TX/RXEQ/RXCDR/SSCG design 3. USB2/USB3 system test/debug/operation

MIPI PHY Circuit Design: 1. MIPI PHY TX/RX for CSI or DSI 2. MIPI PHY RX combo subLVDS/GPIO

1) SAR/ Pipline ADC design 2) Current /R2R DAC design

Power management design: 1) BG design 2) LDO design 3) DC/DC switching power regulator design

1. Develop advanced memory compilers, evaluate new memory architectures and methodologies 2. Perform memory design QA flow and propose continuous improvement plans 3. Provide technical guidance to the memory project reviews

1. Responsible for memory compiler (or instance) development including: create schematic, simulate, verify and analyze memory functionality, performance and statistical margin. 2. Responsible for ASIC project support: memory customization for PPA optimization including: communicate with internal or external customers to evaluate and optimize memory architecture to provide best memory solution.

1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.

1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.

1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.

1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.

1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.

1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.